P-Channel LDO Voltage

[farhad911]

Hi. I'm looking for comments on this P-Channel low drop out voltage circuit I've built. It is working perfectly on the bread board.

Requirements are Input 5.5-15v, Output 5V, 0-2.5 Amps. I've tried with LM358 and it oscillates or doesn't regulate with input past 10V. And I don't have any better op-amps that are rail-to-rail on hand.

What I'm looking for is to know whether what I've built and tested on bread board is good enough, or is there even a better way of doing this. Thanks.

 

[crutschow]

I've tried with LM358

There is no op amp in the schematic you show, so what is the schematic using the LM358?

Below is the simulation of a circuit similar to the one you posted but uses one less transistor.
Not only does this reduce part count, but it reduces the feedback loop gain, thus it is less likely to oscillate.

 

[farhad911]

I've tried these two circuits with LM358. When input increases to 10v or current increases to ~1A, the output either begins to ripple too much or doesn't regulate to 5v at all. However, the inputs were noisier than what I have tested the above on bread board. Since lm358 is not rail-to-rail, I guess that the mosfet's Vg(th) threshold voltage is very important.



And this one. I've never been sure if output resistors should be used with an op amp.



I'll explain why there is a voltage divider on the output of LM358. Since op amp is not rail to rail, I figured that to open and close the NPN BJT around 0.6V base-emitter, the op amp's output should only have to move between 2-4 volts. Is it bad? Thanks.

--Farhad

 

[farhad911]

There is no op amp in the schematic you show, so what is the schematic using the LM358?

Below is the simulation of a circuit similar to the one you posted but uses one less transistor.
Not only does this reduce part count, but it reduces the feedback loop gain, thus it is less likely to oscillate.

View attachment 57075

Yes I first tried with NPN differential pair. I didn't know that it would be more stable though. Why I chose the PNP differential pair above is that it can pull the P-Channel's gate down to almost zero volts. With this npn version, at high currents (~2A), Q1 will be fully on. Assuming that input is 6V, M1's Gate will be a minimum of 2V (divider result of R5,R6). So Vgs would be -4V max. With the PNP version above, Vgs can go all the way down to -6V for better R(ds) On. I managed to reduce R6 to pull the Gate down to ~1.2V but not below 1V. Comes down to design choices now I guess.