I am not concerned about the power then. But low ESR cap thats
means the fet is looking into almost a dead short with 100V across
it, which must be violating SOA if I read the SOA chart right. What is
its ESR ? And for sure the Litiums are low esr as well.
You could run a quick turn on test with a milliohm shunt in the load
path, and using a DSO capture what peak current and Vds looks like
to see what you have.
You could try a compromise when you turn on fet more slowly to get
the cap ramped up slower, that however aggravates power loss in fet.
Or put a constant current limiter in drain of fet to force a ramp. A 3
terminal adjustable reg with a R will handle this -
You lose some head room in Cap V, ~3 V, depending on its leakage.
Regards, Dana.