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Partialy Discharging Capacitor

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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Even with those links, the circuit does not seem complete.
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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It is simply a timing circuit which turns on a very small and wimpy scr.
 

nebojsa

May 13, 2017
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It is simply a timing circuit which turns on a very small and wimpy scr.
I have finally found whole circuit. There is two thyristor and one trigger (switch S2). Can you get some useful info from this circuit? soligor_mk32_sch.png
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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Yeah, now we can see that the gas discharge tube and capacitor (C7) short out the SCR, allowing it to turn off.

So the sequence is:

Place a voltage on the gate of the SCR sufficient to turn it on.

Trigger the main flash tube.

Remove the SCR gate voltage.

Start timing...

At conclusion of the delay, trigger the gas tube surge arrestor. This provides a short duration alternative path for current through the main flash tube. At the conclusion, the SCR is turned off and the flash tube extinguishes.

The duration of the flash is extended by the inductor L1. The diode across it dumps the energy stored in the inductor when the flash tube turns off.

An interesting factor is the combination of C7 and HL3 reduces the rate of rise of voltage across TH1 to prevent dv/dt triggering.
 

nebojsa

May 13, 2017
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Yeah, now we can see that the gas discharge tube and capacitor (C7) short out the SCR, allowing it to turn off.

So the sequence is:

Place a voltage on the gate of the SCR sufficient to turn it on.

Trigger the main flash tube.

Remove the SCR gate voltage.

Start timing...

At conclusion of the delay, trigger the gas tube surge arrestor. This provides a short duration alternative path for current through the main flash tube. At the conclusion, the SCR is turned off and the flash tube extinguishes.

The duration of the flash is extended by the inductor L1. The diode across it dumps the energy stored in the inductor when the flash tube turns off.

An interesting factor is the combination of C7 and HL3 reduces the rate of rise of voltage across TH1 to prevent dv/dt triggering.
Excellent explanation! We can finaly close this discussion. This project is too much complicated for me right now. I will leave it for later. I need to improve myself in understanding of electronics. Anyway thanx for your time, patience and knowledge. :)
 
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nebojsa

May 13, 2017
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