J

#### [email protected]

- Jan 1, 1970

- 0

I'm trying to design a PLL frequency multiplier which will track a

50Hz +- 1Hz sinusoidal signal and generate a clock at a rate of

12.8Khz nominal, synchronised to that signal. (*256 multiplication)

I've got an LM565 phase locked loop and have built a circuit which has

a divide by 256 counter in the feedback loop, similar to the reference

design on page 7 of the datasheet (http://cache.national.com/ds/LM/

LM565.pdf) albeit with different component values and a lead lag

filter .

This circuit works to a point - I've succesfully locked onto the input

signal and am generating a 12.8khz clock which is synchronised to the

input waveform.

However, as I vary the input frequency between 49 and 51hz, there is a

change in phase between the output and the input which can be clearly

seen by comparing pins 2 (input) and 5 (divided signal - input to the

phase detector.)

Someone has said that this is because the LM565 has a type one phase

detector (?) and hence there will always be a phase error which is

dependent on input frequency - is that correct?

For reference, the parameters of the loop are as follows....

Free running frequency - 12.8khz (hand tuned)

Loop Gain 86016 (from datasheet)

Natural Frequency 864hz

Damping factor 1.39

T1 cutoff frequency - 8.45

T2 cutoff frequency - 312.5

If anyone could offer any advice, then I'd be most grateful.

Thanks,

Jim