Network

B

Bob Monsen

Jan 1, 1970
0
Bob said:
[quoted text muted]

I looked, but it doesn't make sense to me. The -FS and +FS ends of
the scale are not symmetrical, with the lowest output transition
taking place at (-FS) +1/2LSB, but the highest transition taking place
at (+FS) -1 1/2 LSB, which can't be correct. Can it?

Yes, that IS correct, I believe. They mention it several times in the
datasheet.

Again, consider a 2 bit ADC. It can transition at 1/8, 3/8, and 5/8.
Voltages then map to output like so:

-1/8 to 1/8 = 0
1/8 to 3/8 = 1
3/8 to 5/8 = 2
5/8 to 1 = 3

If we want to go backwards, we then use

0 = 0
1 = 1/4
2 = 1/2
3 = 3/4

and are assured that we aren't off by more than 1/8. That corresponds to
using 2^N as a divisor.

We can also map the input voltages differently:

-1/6 to 1/6 = 0
1/6 to 3/6 = 1
3/6 to 5/6 = 2
5/6 to 7/6 = 3

Then, the reverse mapping is

0 = 0
1 = 1/3
2 = 2/3
3 = 1

That corresponds to using 2^N-1 as a divisor. This is fine, except that
the transition points are no longer related to the reference voltage by a
power of 2.

I'm guessing that the construction of different types of ADC (and perhaps
the personal preference of the design) influences whether one or the other
mapping scheme is used. For example, a successive approximation ADC is
probably more likely to use the first scheme, because it is probably
easier to generate binary reference levels as the approximation
progresses. However, a flash converter has no such requirements, so the
levels can be set arbitrarily.

--
Regards,
Bob Monsen

The most beautiful experience we can have is the mysterious. It's the
fundamental emotion which stands at the cradle of true art and
science. Whoever does not know it can no longer wander, no longer
marvel, is as good as dead, and his eyes are dimmed.
Albert Einstein (1879 - 1955)

J

John Popelish

Jan 1, 1970
0
Bob said:
Bob Monsen wrote:

[quoted text muted]

I looked, but it doesn't make sense to me. The -FS and +FS ends of
the scale are not symmetrical, with the lowest output transition
taking place at (-FS) +1/2LSB, but the highest transition taking place
at (+FS) -1 1/2 LSB, which can't be correct. Can it?

Yes, that IS correct, I believe. They mention it several times in the
datasheet.

Multiple mentions does not guarantee correctness. Why would the most
positive and most negative transitions not occur symmetrically with
respect to the negative and positive full scale references (-FS and +FS)?
Again, consider a 2 bit ADC. It can transition at 1/8, 3/8, and 5/8.
Voltages then map to output like so:

-1/8 to 1/8 = 0
1/8 to 3/8 = 1
3/8 to 5/8 = 2
5/8 to 1 = 3

You could, I suppose, but why would you design such a thing?

What are the negative and positive full scale values for this series
of decisions?
If we want to go backwards, we then use

0 = 0
1 = 1/4
2 = 1/2
3 = 3/4

Actually,
0= less than +1/8
1= 1/8 to 3/8
2= 5/8 to 5/8
3= greater than 5/8
With the -FS=0 and +FS=6/8

Symmetrical.
and are assured that we aren't off by more than 1/8. That corresponds to
using 2^N as a divisor.

We can also map the input voltages differently:

-1/6 to 1/6 = 0
1/6 to 3/6 = 1
3/6 to 5/6 = 2
5/6 to 7/6 = 3

Then, the reverse mapping is

0 = 0
1 = 1/3
2 = 2/3
3 = 1

Actually,
0= less than 1/6
1= 1/6 to 3/6
2= 3/6 to 5/6
3= greater than 5/6
With -FS=0, +FS=6/6

Still symmetrical.

That corresponds to using 2^N-1 as a divisor. This is fine, except that
the transition points are no longer related to the reference voltage by a
power of 2.

You didn't specify -FS and +FS.
I'm guessing that the construction of different types of ADC (and perhaps
the personal preference of the design) influences whether one or the other
mapping scheme is used. For example, a successive approximation ADC is
probably more likely to use the first scheme, because it is probably
easier to generate binary reference levels as the approximation
progresses. However, a flash converter has no such requirements, so the
levels can be set arbitrarily.

Whether based on resistive R/2R ladders or the capacitive equivalent,
the first and last steps come out half as large as the rest, if valid
inputs are only the voltages between -FS and +FS. If the steps are
based on a single voltage divider with taps (parallel flash
converters), any step arrangement is possible, as long as it is monotonic.

B

Bob Monsen

Jan 1, 1970
0
Bob said:
Bob Monsen wrote:

[quoted text muted]

I looked, but it doesn't make sense to me. The -FS and +FS ends of
the scale are not symmetrical, with the lowest output transition
taking place at (-FS) +1/2LSB, but the highest transition taking place
at (+FS) -1 1/2 LSB, which can't be correct. Can it?

Yes, that IS correct, I believe. They mention it several times in the
datasheet.

Multiple mentions does not guarantee correctness. Why would the most
positive and most negative transitions not occur symmetrically with
respect to the negative and positive full scale references (-FS and +FS)?
Again, consider a 2 bit ADC. It can transition at 1/8, 3/8, and 5/8.
Voltages then map to output like so:

-1/8 to 1/8 = 0
1/8 to 3/8 = 1
3/8 to 5/8 = 2
5/8 to 1 = 3

You could, I suppose, but why would you design such a thing?

Beats me, but that is what the analog guys designed when they designed
the AD9226. The chip has outputs that signal 'out of range', and 'msb'. If
(using the example above) the input is less than -1/8, they set OTR, and
leave MSB 0. If it is greater than 7/8, they set OTR, and also set MSB.
There are 2^12 discrete values that the adc takes on between 0 and +FS,
and when the input gets to +FS, it sets MSB. I do not know if it clears
the output bits at this point...
What are the negative and positive full scale values for this series
of decisions?

They are 0 and undefined.
Actually,
0= less than +1/8
1= 1/8 to 3/8
2= 5/8 to 5/8
3= greater than 5/8
With the -FS=0 and +FS=6/8

Symmetrical.

Well, right, of course. But the point was that if you run an analog input
into an ADC, and then connect that ADC to a DAC, you'll get those output
values. So, in some sense, you can say that the input voltage was those
values, within a margin of error. If you are going to print it out, you
just print the center of the range, right, not both values in the range,
right?
Actually,
0= less than 1/6
1= 1/6 to 3/6
2= 3/6 to 5/6
3= greater than 5/6
With -FS=0, +FS=6/6

Still symmetrical.

You didn't specify -FS and +FS.

I was assuming 0 and 1

--
Regards,
Bob Monsen

He who joyfully marches in rank and file has already earned my
contempt. He has been given a large brain by mistake, since for him
the spinal cord would suffice.
Albert Einstein (1879 - 1955)

J

[email protected]

Jan 1, 1970
0
Bob said:
I was assuming 0 and 1

Okay, let me have a crack at this. Assuming -FS=0V and +FS=1V:

A perfect 4 bit DAC would approximate the -FS to +FS voltage range in 4
steps by outputting exactly:

0V for code 00
1/3V for code 01
2/3V for code 10
3/3v for code11

But a perfect A/D responding to continuous voltages in the range of 0
to 1 would transition between output states at voltages exactly half
way between these 4 voltages (at 1/6, 3/6, 5/6V) to produce codes of:

00 for all voltage less than 1/6V (down to some lower functional lower
limit)
01 for voltages between 1/6V and 3/6V
10 for voltages betwewen 3/6V and 5/6V
10 for all voltages greater than 5/6V up to some higher functional
limit.

If the lower and higher functional limit are 0V and 1V, (very common)
then the first and last votlage range are exactly half as large as all
the ones in the middle.

Thus, (in this case, where n=2) there are 2^n voltages ranges that can
be quantified but there are only (2^n)-1 transistions between those
ranges. The span from -FS to +FS is divided into steps of voltage that
are all (+FS-(-FS))/((2^n)-1) {=1/3, in the case where n=2}, except
for the first and last which are (+FS-(-FS)/(((2^n)-1)/2) {=1/6, in
the case where n=2}.

Why would anyone design a real linear DAC or A/D to do something else?

B

Bob Monsen

Jan 1, 1970
0
Bob said:
[quoted text muted]

Okay, let me have a crack at this. Assuming -FS=0V and +FS=1V:

A perfect 4 bit DAC would approximate the -FS to +FS voltage range in 4
steps by outputting exactly:

0V for code 00
1/3V for code 01
2/3V for code 10
3/3v for code11

The AD5424 is an 8 bit DAC. Here is the datasheet.

The unipolar output function is defined in table 7 as

0 -> 0V
1 -> (1/256)V
2 -> (2/256)V
....
255 -> (255/256)V

The bipolar output function is defined in table 8 as

0 -> -(128/128)V
1 -> -(127/128)V
....
0x80 -> 0
0xFF -> (128/128)V

Which has the same output mapping function.

Thus, the output function is Vout=digital_in*Vref/(2^N). They say this
explicitly in the tables above. This is different from your mapping
function of Vout = digital_in * Vref/(2^N - 1)
But a perfect A/D responding to continuous voltages in the range of 0
to 1 would transition between output states at voltages exactly half
way between these 4 voltages (at 1/6, 3/6, 5/6V) to produce codes of:

00 for all voltage less than 1/6V (down to some lower functional lower
limit)
01 for voltages between 1/6V and 3/6V
10 for voltages betwewen 3/6V and 5/6V
10 for all voltages greater than 5/6V up to some higher functional
limit.

I assert that it depends on the type. The three or four ADC devices I
way from your example. They transition to 1 at 1/8, 2 at 3/8, and 3 at
5/8. I was not able to find an ADC that transitions at 1/6, 1/3, and 5/6.
If the lower and higher functional limit are 0V and 1V, (very common)
then the first and last votlage range are exactly half as large as all
the ones in the middle.

Thus, (in this case, where n=2) there are 2^n voltages ranges that can
be quantified but there are only (2^n)-1 transistions between those
ranges. The span from -FS to +FS is divided into steps of voltage that
are all (+FS-(-FS))/((2^n)-1) {=1/3, in the case where n=2}, except
for the first and last which are (+FS-(-FS)/(((2^n)-1)/2) {=1/6, in the
case where n=2}.

Why would anyone design a real linear DAC or A/D to do something else?

It is probably easier to design them the other way? I don't really know. I
just know that the few data sheets I've read, from analog and
linear, indicate that they are doing it so that the output to voltage
function is out*Vref/N.

I am not claiming to be an expert, I've just been looking at them recently
for a project I'm doing. It may be that the majority of them do it the
other way, and that I've just been lucky, so to speak, in the devices I've
looked at.

--
Regards,
Bob Monsen

My life is a simple thing that would interest no one. It is a known
fact that I was born and that is all that is necessary.
Albert Einstein (1879 - 1955)

R

Rich Grise

Jan 1, 1970
0
Bob said:
[quoted text muted]

Okay, let me have a crack at this. Assuming -FS=0V and +FS=1V:

A perfect 4 bit DAC would approximate the -FS to +FS voltage range in 4
steps by outputting exactly:

0V for code 00
1/3V for code 01
2/3V for code 10
3/3v for code11

The AD5424 is an 8 bit DAC. Here is the datasheet.

The unipolar output function is defined in table 7 as

0 -> 0V
1 -> (1/256)V
2 -> (2/256)V
...
255 -> (255/256)V

The bipolar output function is defined in table 8 as

0 -> -(128/128)V
1 -> -(127/128)V
...
0x80 -> 0
0xFF -> (128/128)V

Either it's a typo, or their transfer function changes from
0x80 to 0xFF. ;-)

(I get '0xFF -> (127/128)V' )

Cheers!
Rich

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