- Jan 1, 1970
Bob said:[quoted text muted]
I looked, but it doesn't make sense to me. The -FS and +FS ends of
the scale are not symmetrical, with the lowest output transition
taking place at (-FS) +1/2LSB, but the highest transition taking place
at (+FS) -1 1/2 LSB, which can't be correct. Can it?
Yes, that IS correct, I believe. They mention it several times in the
Again, consider a 2 bit ADC. It can transition at 1/8, 3/8, and 5/8.
Voltages then map to output like so:
-1/8 to 1/8 = 0
1/8 to 3/8 = 1
3/8 to 5/8 = 2
5/8 to 1 = 3
If we want to go backwards, we then use
0 = 0
1 = 1/4
2 = 1/2
3 = 3/4
and are assured that we aren't off by more than 1/8. That corresponds to
using 2^N as a divisor.
We can also map the input voltages differently:
-1/6 to 1/6 = 0
1/6 to 3/6 = 1
3/6 to 5/6 = 2
5/6 to 7/6 = 3
Then, the reverse mapping is
0 = 0
1 = 1/3
2 = 2/3
3 = 1
That corresponds to using 2^N-1 as a divisor. This is fine, except that
the transition points are no longer related to the reference voltage by a
power of 2.
I'm guessing that the construction of different types of ADC (and perhaps
the personal preference of the design) influences whether one or the other
mapping scheme is used. For example, a successive approximation ADC is
probably more likely to use the first scheme, because it is probably
easier to generate binary reference levels as the approximation
progresses. However, a flash converter has no such requirements, so the
levels can be set arbitrarily.
The most beautiful experience we can have is the mysterious. It's the
fundamental emotion which stands at the cradle of true art and
science. Whoever does not know it can no longer wander, no longer
marvel, is as good as dead, and his eyes are dimmed.
Albert Einstein (1879 - 1955)