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Please explain circuit

dorke

Jun 20, 2015
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@dork Again, I get how it works. My mind thinks of it as "positive needs to make its way to pin 14 in order for it to trigger clock and increment its outputs.
So, your saying the correct way to say it is; "1 level" instead of "power"?

Yes absolutely !
or " logic 1"
 

AnalogKid

Jun 10, 2015
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@dork Again, I get how it works. My mind thinks of it as "positive needs to make its way to pin 14 in order for it to trigger clock and increment its outputs.
So, your saying the correct way to say it is; "1 level" instead of "power"?
or a "logic 1", yes.

ak
 

dorke

Jun 20, 2015
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@AK,
You are wrong here again.
There is feedback.look better.

Anyways,why do you think the feedback should be
"each stage -Q output back to its D input" ,where does this come from!

It isn't a shift register!
 
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Chemelec

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(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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You are wrong here again.

Actually he's right.

"Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter."

http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register07.html

Incidentally, another important characteristic of twisted ring counters is that they are able to be clocked very rapidly due to the fact that only a single flip flop changes state during any transition.

I have seen them used as pre-scalers for frequency counters.

One of the important things about the 4017 is that the clock input is a Schmitt trigger. So the addition of a capacitor across the pulldown resistor for the clock input should do all that is needed to debounce the button(s).
 

AnalogKid

Jun 10, 2015
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why do you think the feedback should be "each stage -Q output back to its D input" ,where does this come from!
Some counters are shown with D flipflops internally, and some are shown with JK flipflops. These are just variations on a theme, and both require some form of feedback to toggle with each clock edge. With JK's it is internal. Often it is shown explicitly with D flipflops.

ak
 

hevans1944

Hop - AC8NS
Jun 21, 2012
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Hop,
"As for switch bounce, the first "legal" transition that results in a valid clock pulse will advance the counter and remove the voltage to the switch. Who cares if the switch contacts bounce after that?"

No that thinking is absolutely wrong(both in theory and in practice) !!!

The voltage is "removed" from the output in a non-zero time interval.
For the CD4017 (which is a very slow digital device,Fairchild datasheet )
it can be more than 400nSEC @9V, and 1000nSec @5V.

In that 0.4uSEC the voltage to the switch is still "1", if the switch bounces in that time interval,
we may get false clocking!

The minimum tW for the CK line is 90nSec .
So, we can get up to 400/90 => 4 ,"0" and "1" legal clock levels on the CK line
that is equivalent to 2(or 3) legal clock positive edges.
For non "legal", but still ones that may advance the counter, we can get much more.


My diagram show it clearly let me put in the numbers for you:
View attachment 29702
You may be right, dorke, but it would take a really fast bouncing switch to make multiple bounces in the interval between the first low-to-high transition of the clock input that advances the counter and the resulting change in the decoded output from logic 1 to logic 0 that removes "power" to the switch. It's possible, of course, since this "design" does not specify a particular switch. I generally abhor "designs" that do not take switch contact bounce specifically into account.

I agree that if the bounces occur in the interval between the first low-to-high clock transition and when the decoded output changes from logic 1 to logic 0 (caused by propagation delay in the decoder logic), then internally the Johnson counter could advance multiple times before the decoded output changed. Not a good thing if the decoded outputs change from, say, Q0 = 1 to Qn = 1, where Qn is NOT Q2. That would totally mess up the "password" decoding.

You can deliberately make this happen by adding a small capacitor to common at the connection between the diode cathode and the switch contact to produce clock pulses from each switch bounce after the button is pressed. The capacitor continues to provide the "supply" voltage to the switch after the first clock pulse causes the decoded output to (eventually) go low. This lasts until the capacitor is discharged, through the 100 kΩ resistor connected from the clock input to common, to a voltage less than required to clock the counter. So ordinary switches that take a few microseconds to mechanically bounce can now produce erroneous results. :D

However, as I said earlier, I have not built this circuit. It may work fine if the switch bounces only occur after the decoded output goes from logic 1 to logic 0 and you don't add any capacitors. I think a capacitor from the clock input to common will not improve matters.

BTW, only the Phillips Semiconductor HEF4017B datasheet states that clock inputs have Schmitt-trigger conditioning, although this would be typical for the rather longish 5 to 20 μs rise and fall times allowed (depending on supply voltage). The TI, NXP, and Fairchild datasheets don't mention Schmitt-trigger signal conditioning for the clock inputs.
 

dorke

Jun 20, 2015
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Hop,Agree with you .
Like we said before it's a Bad design...and has such,
it is good methodology and practice to avoid such.
Nevertheless , it can still work,it all depends on the switch type/behavior.

The problem of switch bouncing can be "properly solved" by introducing a dedicated HW switch de-bouncer.

Now-days a lock is a job tailored for a small uC(with them being so cheap),
using software de-bouncing .
It will give total flexibility:
code length,code changing,number of trails allowed etc.
 

hevans1944

Hop - AC8NS
Jun 21, 2012
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Since this thread started a discussion of cipher locks, I am seriously thinking about using a microprocessor to build the "random character display with telephone keypad" lock that I described in post #10. I thought it was way cool when I used it sometime in the 1990s. My problem is building the display box that prevents anyone nearby seeing the locations of the random character positions. And I don't know what I would use to display # and * symbols. I suppose I could just not use those two symbols, or maybe use 7-segment displays and use + and - symbols to represent the # and * symbols on a common telephone keypad. Yeah, that's what I will do!

IIRC, the display I saw at the jet engine test cell facility used Nixie tubes! I remember the orange color. But I don't know where to get any Nixies with # and * grids inside in addition to the usual 0 through 9 grids. Maybe dot-matrix displays would work okay, but that seems needlessly complicated to just display two special characters. So + and - symbols will be used to represent the # and * on a standard telephone keypad.

OTOH, an LCD character display would also be feasible and fairly easy to interface to a μP. I happen to have an LCD "shield" I purchased at Radio Shack for Arduino Uno, so now I have an excuse to learn how to use it! :D And somewhere I have a black honeycomb air filter, about a half-inch thick, that I can use to obscure the display from off-angle viewing.

Now where did I put that matrix-scanned telephone keypad? Yikes! Might have to actually purchase something, besides a solenoid-activated dead-bolt door lock. I plan to use this new electronic cipher lock to first enable and disable an alarm system for my house, retaining the key-operated dead-bolt door lock for now. Good quality solenoid-operated door locks are still a bit pricey.

I will start a new thread and post progress reports if this project actually moves beyond the concept design stage. :cool: @chopnhack isn't the only one here who can over-engineer a project and take two plus years to build it! But then, he started from ground zero with almost no knowledge of electronics, and his final result was excellent. With my advanced training and experience I should be able to complete the Cipher Lock Project in five years, plus or minus... depending on how many engineering change orders (ECOs) occur. :rolleyes:

Hop - AC8NS
 
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