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PLL loop filter design

Hello,

I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?
 
A

Andrew Holme

Jan 1, 1970
0
Hello,

I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?

I normally express open loop gain in terms of the Laplace 's' operator, and
generate Bode plots using SCILAB. I adjust the various parameters, keeping
an eye on gain and phase margins, to optimise performance.

Download SCILAB from www.scilab.org

Try running this script:

c1 = 680e-12;
c2 = 100e-12;
r = 1800;
kvco = 2e6;
kpd = 0.5e-3;
s = poly(0,'s');
f = 1/s/c1 * (1+s*r*(c1+c2)) / (1+s*r*c2);
g = kpd * f * kvco/s;
g = syslin('c', g);
xbasc(0);
bode(g, 1e3, 1e7, .01);

You can also plot closed loop gain, step response and much more.
 
M

MooseFET

Jan 1, 1970
0
I normally express open loop gain in terms of the Laplace 's' operator, and
generate Bode plots using SCILAB. I adjust the various parameters, keeping
an eye on gain and phase margins, to optimise performance.

Add noise to that list.

Watch the noise voltage at the control input of the VCO.

Dont do this:

---/\/\-----+-------/\/\-------+--------VCO
! !
--- C(small) \
--- /
! \
GND !
---
---
!
GND

Do do this:

--------------------/\/\-------+----+---VCO
! !
\ ---
/ --- C(small)
\ !
! GND
---
---
!
GND

Even though they can have the same phase margin, the lower one has a
low impedance on the VCO's control input, at frequencies above the
gain cross over.
 
R

Rene Tschaggelar

Jan 1, 1970
0
Hello,

I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?

I can recommend the PLL designer available for
download at the Analog Devices website. A key
figure is the steepness of the slope of the VCO.
How many MHz/volts does ist make and is it
moreless linear ? Then, a key part is the operational
amplifier for the filter. The Analog Device designer
shows how the input bias current influences the
performance of the loop.

Rene
 
T

Tom Bruhns

Jan 1, 1970
0
Hello,

I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?

In addition to the advice from Andrew and MooseFET, I'd suggest you
download the free PLL design software from the Analog Devices web
site. It takes a lot of the work out of PLL design. I'll caution
that no software I know of is a substitute for engaging your brain,
but it can at least be very helpful for gaining insights into how
things work. For example, the software won't TELL you what loop
bandwidth to use. You have to think carefully about that, and make an
intelligent choice based on your requirements and the characteristics
of the VCO, reference, and the rest of the circuit.

(Having just designed a loop not too different from what you describe,
I can say I'm surprised by the femtofarad value. I'd expect with a
very narrow tuning range that you would implement a loop with narrow
bandwidth, and that should have relatively large capacitances in it.
My problem is more commonly finding physically small microfarad-size
caps that have very low dielectric absorption and low noise.)

Cheers,
Tom
 
J

John Larkin

Jan 1, 1970
0
Hello,

I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?

We recently did this, locking a 40 MHz VCXO to an external 10 MHz
reference. We divided the 40 down to 10, xor'd it with the external
input (both in an FPGA) and used a simple r-c lowpass from the xor
output to the VCXO control input. So the whole phase locked loop costs
a few cents. Just figure out the natural loop unity-gain frequency and
set the r-c rolloff to be, say, 10x that... typically on the order of
a few KHz rolloff for a VCXO. You get a bulletproof first-order loop
and excellent phase noise behavior.

This works because your maximum possible error frequency is small, so
acquisition range is not a problem.

John
 
I can recommend the PLL designer available for
download at the Analog Devices website.

Hm, I found only ADIsimPLL, and I can't choose
different phase detectors and I don't see how to input
other values.
A key
figure is the steepness of the slope of the VCO.
How many MHz/volts does ist make and is it
moreless linear ? Then, a key part is the operational
amplifier for the filter. The Analog Device designer
shows how the input bias current influences the
performance of the loop.

Pure VCO without any amplifier may be tuned from 69.999.975 Hz
(Vtune=0V) to
70.000.025 Hz (Vtune=12V), with good linearity. With constant Vtune
output frequency from VCO is quite stable,
it changes about 5-10Hz during 10min. period.
I think that I'll use a simple passive lag filter like this:

R1
----/\/\/\/\/\-----+---------
|
|
/
\ R2
/
\
/
|
|
|
___ C
___
|
|
|
GND


with inverting opamp amplifier with gain=10 connected to the output of
this filter
(becouse output from phase detector is negative). So, pure Kvco is
4.16 Hz/V and
with opamp amplifier it will be 41.6 Hz/V = 130 rad/Vs. From RPD-2
datasheet we know, that
Kd = 8mV/deg = 0.460V/rad. I choose damping factor at xi=0.707. For
this type of filter,
we have relations (I took it from E. Best book):

1: tau_1 = R1C
2: tau_2 = R2C

3: w_n^2 = Kvco*Kd/(tau_1 + tau_2)
4: xi=0.5 * w_n (tau_2 + 1/(Kvco*Kd))

where w_n is a natural frequancy and it will be w_n=31.4 rad/s
(=10Hz). From 4th relation we
have tau_2=0.0276 s, and from 3rd we have tau_1=0.061 s. These values
are reasonable,
E. Best wrote in his book, that tau_1 should be about 5 to 10 times
larger than tau_2.
I assume, that 100k for R1 will be a good choice. From 1st relation we
have C=61nF, and from 2nd R2=450k.
And finally, filter looks like this:


R1
--|----/\/\/\/\/\-----+---------
| |
| |
\ /
/ \ R2
\ 500 /
/ \
\ /
| |
| |
| |
| ___ C
| ___
| |
| |
GND |
GND


Parallel resistor (500 Ohm) at the input is for impedance match
(output impedance of RPD-2
phase detector is 500 Ohm). Are this calculations correct?
 
(Having just designed a loop not too different from what you describe,
I can say I'm surprised by the femtofarad value. I'd expect with a
very narrow tuning range that you would implement a loop with narrow
bandwidth, and that should have relatively large capacitances in it.

I see now, that I made a stupid mistakes when I calculated this, I
used some
loop filter calculator without thinking :)
My problem is more commonly finding physically small microfarad-size
caps that have very low dielectric absorption and low noise.)

For narrow bandwidth loops? I heard that for such a loops digital
filters
(ADC->some computations->DAC) are much better than a ordinary RC
filters,
because for example capacitor capacity may change with age and ambient
temperature.
 
Are this calculations correct?


A little supplement: I made a miscalculation, proper values are:
Kvco=260 rad/Vs, Kd=0,46 V/rad, w_n=62.8 rad/s, tau_1=0.03s,
tau_2=0.014s
R1=100k, R2=46k, C=300nF.
 
T

Tom Bruhns

Jan 1, 1970
0
I see now, that I made a stupid mistakes when I calculated this, I
used some
loop filter calculator without thinking :)


For narrow bandwidth loops? I heard that for such a loops digital
filters
(ADC->some computations->DAC) are much better than a ordinary RC
filters,
because for example capacitor capacity may change with age and ambient
temperature.

I would expect the loop to be stable enough--to have enough margin--
that small changes in capacitance wouldn't make much difference. Even
as long as the temperature changes are not abrupt, things should be
fine. But there are other characteristics I do worry about. Size is
one. I'm not sure I could make a digital filter as small as the
analog, but it's a good thought. Fortunately, C0G multilayer ceramics
(which are quite stable over temperature and time and voltage, and
have low dielectric absorption) are available these days up to rather
large values, as are tiny op amps with low input bias current.

I can see that a nearly-all-digital solution would make sense for some
applications, though probably not for mine, which isn't all that
narrow a loop bandwidth. Thanks for the suggestion.

Cheers,
Tom
 
T

Tom Bruhns

Jan 1, 1970
0
Hm, I found only ADIsimPLL, and I can't choose
different phase detectors and I don't see how to input
other values.


Pure VCO without any amplifier may be tuned from 69.999.975 Hz
(Vtune=0V) to
70.000.025 Hz (Vtune=12V), with good linearity. With constant Vtune
output frequency from VCO is quite stable,
it changes about 5-10Hz during 10min. period.
I think that I'll use a simple passive lag filter like this:

R1
----/\/\/\/\/\-----+---------
|
|
/
\ R2
/
\
/
|
|
|
___ C
___
|
|
|
GND

with inverting opamp amplifier with gain=10 connected to the output of
this filter
(becouse output from phase detector is negative). So, pure Kvco is
4.16 Hz/V and
with opamp amplifier it will be 41.6 Hz/V = 130 rad/Vs. From RPD-2
datasheet we know, that
Kd = 8mV/deg = 0.460V/rad. I choose damping factor at xi=0.707. For
this type of filter,
we have relations (I took it from E. Best book):

1: tau_1 = R1C
2: tau_2 = R2C

3: w_n^2 = Kvco*Kd/(tau_1 + tau_2)
4: xi=0.5 * w_n (tau_2 + 1/(Kvco*Kd))

where w_n is a natural frequancy and it will be w_n=31.4 rad/s
(=10Hz). From 4th relation we
have tau_2=0.0276 s, and from 3rd we have tau_1=0.061 s. These values
are reasonable,
E. Best wrote in his book, that tau_1 should be about 5 to 10 times
larger than tau_2.
I assume, that 100k for R1 will be a good choice. From 1st relation we
have C=61nF, and from 2nd R2=450k.
And finally, filter looks like this:

R1
--|----/\/\/\/\/\-----+---------
| |
| |
\ /
/ \ R2
\ 500 /
/ \
\ /
| |
| |
| |
| ___ C
| ___
| |
| |
GND |
GND

Parallel resistor (500 Ohm) at the input is for impedance match
(output impedance of RPD-2
phase detector is 500 Ohm). Are this calculations correct?

I have not checked the calculations, and I'm just assuming the values
are right. Just wanted to point out that noise may be a
consideration. Such large resistor values may add noticably to the
noise. Of course, as you go to smaller resistor values, the capacitor
value increases, and that may be a problem. If you have plenty of
space, consider, say, a 1uF polypropylene part. Then the resistor
values would scale to give you about 1/4 as much resistor noise.

Also, with a passive filter, will your phase comparator be able to
drive it to the full voltage range you need for the VCO? One reason
to use an op amp based filter is to get some voltage gain--to increase
the maximum output voltage range.

Cheers,
Tom
 
C

Chris Jones

Jan 1, 1970
0
John said:
We recently did this, locking a 40 MHz VCXO to an external 10 MHz
reference. We divided the 40 down to 10, xor'd it with the external
input (both in an FPGA) and used a simple r-c lowpass from the xor
output to the VCXO control input. So the whole phase locked loop costs
a few cents. Just figure out the natural loop unity-gain frequency and
set the r-c rolloff to be, say, 10x that... typically on the order of
a few KHz rolloff for a VCXO. You get a bulletproof first-order loop
and excellent phase noise behavior.

This works because your maximum possible error frequency is small, so
acquisition range is not a problem.

John

The OP could also try an ADF4001 which I have used for a similar purpose. I
used the ADISimPLL program to design the loop filter. They seem to have a
new version that I have not tried.
http://forms.analog.com/form_pages/rfcomms/adisimpll.asp
A microcontroller or similar would be needed to put the frequency division
ratios into the ADF4001.

Chris
 
The OP could also try an ADF4001 which I have used for a similar purpose. I
used the ADISimPLL program to design the loop filter. They seem to have a
new version that I have not tried.http://forms.analog.com/form_pages/rfcomms/adisimpll.asp
A microcontroller or similar would be needed to put the frequency division
ratios into the ADF4001.

There is a small problem in this IC: phase detector works on very low
frequency
(REF IN and RF IN signals are divided and after this operation are
mixed in digital
phase detector). For phase noise issue, I want to mix these signals on
high
frequency (in double balanced mixer or in fast digital phase detector,
for example AD9901).
 
T

Tim Shoppa

Jan 1, 1970
0
(Having just designed a loop not too different from what you describe,
I can say I'm surprised by the femtofarad value. I'd expect with a
very narrow tuning range that you would implement a loop with narrow
bandwidth, and that should have relatively large capacitances in it.

Seems likely he confused the VCO frequency with loop bandwidth.

I thought things got bad when folks started punching numbers into
pocket calculators without any regards for what they meant - computers
make the problem worse. The not-otherwise-encountered units found in
loop filter calculations (volts per radian and radians per volt both
represented by a capital K) often confuse folks the first time around!

Tim.
 
J

John Larkin

Jan 1, 1970
0
There is a small problem in this IC: phase detector works on very low
frequency
(REF IN and RF IN signals are divided and after this operation are
mixed in digital
phase detector). For phase noise issue,

Right. The big division magnifies phase noise.

I want to mix these signals on
high
frequency (in double balanced mixer or in fast digital phase detector,
for example AD9901).

Once an AD9901 walks the VCO into lock, it becomes an xor. So if you
don't have a large acquisition range problem, save a lot of money and
hassle and just use a 20-cent xor.

John
 
J

Jim Thompson

Jan 1, 1970
0
Right. The big division magnifies phase noise.



Once an AD9901 walks the VCO into lock, it becomes an xor. So if you
don't have a large acquisition range problem, save a lot of money and
hassle and just use a 20-cent xor.

John

The big boys go "fractional-N".

...Jim Thompson
 
C

Chris Jones

Jan 1, 1970
0
There is a small problem in this IC: phase detector works on very low
frequency
(REF IN and RF IN signals are divided and after this operation are
mixed in digital
phase detector). For phase noise issue, I want to mix these signals on
high
frequency (in double balanced mixer or in fast digital phase detector,
for example AD9901).

I was not aware that the OP required a frequency ratio that would
necessitate a low comparison frequency, and if the OP did require a low
comparison frequency then a simpler phase detector would not solve the
problem. (I have never seen the complete original post since someone
trimmed it away.) Unless the OP requires a nasty frequency ratio between
the reference input and the VCO output, the ADF4001 would allow high
comparison frequencies. The reference and feedback dividers can divide by
numbers as low as 1, so it could do just as high a comparison frequency as
any other integer-N synth could do, (up to the limit imposed by the spec,
obviously).

Chris
 
G

Gerhard Hoffmann

Jan 1, 1970
0
Once an AD9901 walks the VCO into lock, it becomes an xor. So if you
don't have a large acquisition range problem, save a lot of money and
hassle and just use a 20-cent xor.

OK, the AD9901 is not low cost and quite hot, but it is fast, reasonably low-noise
and moves that Kpd wobble away from the lock point.
I really liked it.

regards, Gerhard
 
C

Chris Jones

Jan 1, 1970
0
There is a small problem in this IC: phase detector works on very low
frequency
(REF IN and RF IN signals are divided and after this operation are
mixed in digital
phase detector). For phase noise issue, I want to mix these signals on
high
frequency (in double balanced mixer or in fast digital phase detector,
for example AD9901).

You can program the dividers in the ADF4001 to divide by ratios down to 1,
so it is no worse than any other integer-N PLL in that respect.

Chris
 

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