E
[email protected]
- Jan 1, 1970
- 0
Hello,
I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?
I'm trying to design a loop filter for PLL. I have a stable reference
signal (RF REF=70 MHz) and output from VCO (RF IN=70 MHz, but very
small tunnig range, few Hz). I want to synchronize my VCO with RF REF
(this freq. won't be changed, all freqs. are fixed). Levels of these
signals are about +7dBm, and this is sufficient for MiniCircuits RPD-2
phase detector. I tried to desing filter according to simple guide in
R. Best "Phase-Locked Loops" but I had a stange values (for example
capacitance in femtofardars). Any hints how to start?