Power on reset circuit

[Karthik rajagopal]

Hi all,
I started working with flip flop where I encountered a problem of the flip flops entering a random state on power up. So, I built a power on reset circuit with a 10uF and a 1k resistor. My circuit contains two different sections where on part has JK flip flops with negative reset trigger and D flip flops with positive reset trigger. So I connected my power on reset circuit to D flip flops directly and to JK flip flops through an inverter. Since the reset lasts for 10ms, the inverter's (NOT gate) propagation delay creates an output mismatch between the two sections of the circuit. I also tried using an NPN transistor in place of a NOT gate which didn't improve the situation. Please suggest me a way to solve this problem.
Thanks in advance.

 

[Harald Kapp]

There is no way you can eliminate this mismatch when using any kind of inverter (logic gate, transistor, whatever). You can only minimize it by using a very fast inverterr.
But first you'll have to consider whether this delay (a few ns at best) is of importance at all. If you delay the onset of the clock signal longer than the reset duration for the flip-flops, the latter will all have reached a stable state before clock starts.
Plus the effect will depend very much on the type of circuit (synchronous or asynchronous) and the specific implementation. I'm afraid we cannot give a general rule here.

 

[Karthik rajagopal]

There is no way you can eliminate this mismatch when using any kind of inverter (logic gate, transistor, whatever). You can only minimize it by usin a very fast inverterr.
But first you'll have to consider whether this delay (a few ns at best) is of importance at all. If you delay the onset of the clock signal longer than the reset duration for the flip-flops, the latter will all have reached a stable state before clock starts.
Plus the effect will depend very much on the type of circuit (synchronous or asynchronous) and the specific implementation. I'm afraid we cannot give a general rule here.

I connected the clock reset to the reset of the JK flip flop circuitry as you said which had the clock signal going only after the circuit reached a stable state. Thanks for giving me the solution, it finally works as intended.