David said:
You don't really calculate anything, you just follow best practice
design rules.
For each device in your design read the datasheet and app notes to see
what they recommend. Many big (FPGAs for instance) and high speed
devices have very specific requirements, they will tell you all about
in the datasheets and app notes. Disobey manufacturers recommendations
at your own peril.
If nothing is mentioned then it's probably not that critical, in which
case you'd genrally use a single 10nF cap for each device if you have
the room and cost budget available, just to be safe. Although you can
probaly get away with big power planes and the distributed capacitance
in a lot of cases, with just a few caps sprinkled over the place in the
more critical areas.
I'm sure other will elaborate further on the general concept of
decoupling, and there is plenty of info out there on it, Google is your
friend. Suffice it to say that decoupling is a bit of a "black art" and
there are no hard and fast rules that work every time, every design
will have different requirements. Follow general guidelines and you
will usually be fine.
Dave
Well, you can calculate it (at least to a decent first approximation),
but you have to keep ESR, ESL and Z(f) all in mind.
In some very high speed systems, there are specific known frequencies
that will occur. The OP doesn't give enough details to help on that,
though.
The last *really* highspeed system I designed was set for DDR
Infiniband (the switch board had 384 5Gb/s diff pairs
and the
decoupling was primarily for the logic clock in the switches (at least
around those devices) and appropriate harmonics. [The backplane had
2304 IB pairs apart from any other signals]. I decoupled the IB signal
noise by series ferrites along with caps, and the IO buffers had their
own power - the outputs were CML which made life a little bit easier.
For a first approximation for decoupling (at least to see what Z has to
be) I get the effective local impedance of the power system (simply
Vchip / Ichip) and divide by 10 - that's the max impedance I want to
see in the decoupling system to ground for capacitive decoupling. For a
high current, low voltage device (pretty typical in a highspeed
environment), that can make decoupling quite an interesting exercise.
For a 1.2V, 12A device (which is pretty close to what I was using) that
yields 10 milli ohm effective impedance max for that device (at the
various frequencies of interest) requirement for decent decoupling.
It's not incredibly scientific, but it gives me an idea of what I am
looking at. On really highspeed stuff, I also make a distributed
decoupler by having the local power and ground for a device on adjacent
planes, and in a high layer count board, that can yield some pretty
effective decoupling.
Given that decoupling at high frequencies is a very localised affair,
this trick works and I am aware it's hardly thoroughly scientific.
Much depends on just what the OP considers 'high speed', of course.
Cheers
PeteS
