Problem with 8255 PIO design

[mmm]

Yes, that would be an interesting option. Unfortunately we're on a
tight time line and redesigning the circuit would make us loose 1-2
weeks.

We found a different solution that does not require electronic
modifications.

Port A, which we need to be bidirectional, is set to output all the
time. According to Intel (and 3rd party clones seem to match) the
"read" operation on that port always returns the physical state on
these pins, not any internal shadow register or similar. So, when
pulling the pins to high or to low, the state returned by the "read"
operation will follow it instead of the voltage applied by the 8255
itself. With other words, we just have to "read" or "write" to the
port without changing it's direction.

It may be more clear to you if you look at the "schematic" for the
pins on port A. See http://www.dsi.unifi.it/~nesi/8255.pdf at page 4.

I'm a software engineer, not a electronics specialist, (and the idea
wasn't mine) but you probably will see immediately how the components
will play together in the described configuration.

We tried this trick and it works well.

Of course we might change the schematics design for the next version
for which we have a couple of additional weeks to prepare. I like the
FPGA idea but we don't have neither the tools nor the knowledge to
program a FPGA. Our partner company which designs our boards doesn't
either. Once a engineer designed a FPGA for us (different project) but
it was a nightmare and didn't work as expected.

check on the atmel site for ATF15xx family of CPLD:
available on PLCC 44 package , free developing/programming SW, simple
PARALLEL/JTAG programming interface with schematics available
some examples circuits ( amongs other there is an 'improved 8255' )

 

[Joel Kolstad]

Of course we might change the schematics design for the next version
for which we have a couple of additional weeks to prepare. I like the
FPGA idea but we don't have neither the tools nor the knowledge to
program a FPGA.

You'll probably like them a lot if you have a chance to get familiar with
them.

Once a engineer designed a FPGA for us (different project) but
it was a nightmare and didn't work as expected.

In all likelihood this was a result of the engineer's lack of
experience/skills/whatever than a problem with the FPGA technology itself.

I'm glad to hear you managed to get the 8255 solution working.

 

[Rich Grise]

We can't program FPGAs and unfortunately I know no alternative to the
8255 chip. Do you perhaps?

You _could_ program FPGAs (and/or CPLDs) if you got a development kit
for about $100.00; writing an 8255 replacement in VHDL or Verilog should
be easy and fun!

Or, for that matter, (at least in the Xilinx package I have) you can do
schematic entry.

Have Fun!
Rich

 

[Frank Buss]

Any can propose a workaround for this? Since we want to avoid adding
much additional logic: Is there a similar near-24 bit I/O chip that
would be useful for our needs?

If you have an I2C port on your board, you can use this chip:

http://www.nxp.com/acrobat_download/datasheets/PCA9555_7.pdf

If you don't have an I2C port or there are other problems with the chip,
you can use an CPLD. I've implemented the functions of the 9555 in VHDL as
an example how to use my I2C VHDL implementation:

http://www.frank-buss.de/vhdl/i2c_slave-0.4.zip

You could drop the I2C part and add an ISA interface, which should be not
too difficult.

But using a FPGA would be overkill for such a simple project, use a CPLD.
There are chips with on-chip flash (most FPGAs need an external flash for
programming at power on) from Xilinx and Altera, like the MAX II from
Altera, which you can buy for 5 euro (the smallest part should work for a
8255 replacement). There is even a development kit with a PCI interface:

http://www.altera.com/products/devkits/altera/kit-maxii-1270.html

but you can get cheaper development kits for it, too:

http://tinyurl.com/3b54ov

Software is free for this part from Altera (same for many Xilinx chips).

 

[Sambo]

Hi,

we wanted to use the 8255 for a relatively simple design. It seemed
that the 8255 has three independent 8bit I/O ports so we used one port
for a (slow) bi-directional bus and the other ports for other
purposes. We already have the prototype but the design is invalid
because of this one little sentence in the whole data sheet:

"Any port programmed as an output port is initialized to all zeros
when the control word is written."

So, when we want to toggle the *direction* of port A (the one used for
the bidirectional bus), all *outputs* of ports B and C will be reset
as well! This makes the 8255 completely useless for our purposes (we
need the other outputs to stay unchanged).

It doesn't say all ports are reset?
Although it may work that way.

 

[Rich Grise]

It doesn't say all ports are reset?
Although it may work that way.

Yes; the 8255 is crap. You'd be much better off to get an FPGA or a
CPLD and write your own functions.

Cheers!
Rich

 

[Sambo]

need the other outputs to stay unchanged).

Yes; the 8255 is crap. You'd be much better off to get an FPGA or a
CPLD and write your own functions.

Cheers!
Rich

I was always nostalgic about the 6526 because of it's ability to configure I/O individually for each bit, until now, that I can do this with PICs.
Just started playing with 16bit 18F2320 and it even has separate ('software')
registers for write and read buffers. Too bad I took so long to give pics a try.
OOOH baby.... HEH.

Cheers.