In the saturation region, why does Ic increase with an increase in Vce?
In the active region, does the graph indicate that a specific base current only provides a specific collector current (that is, Ic=Ib * Beta)?
This is one example of a real device versus an ideal one. Examine the graph and you'll see that Ic increases very rapidly with a small change in Vce in the saturation region. In an ideal device, any Vce greater than zero would suffice, but in a real device the physics of the junctions require some Vce. In practice you typically don't want the Vce to swing too close to the Vce(sat) specification.
Basically correct. Once the transistor is in the active region the collector current (Ic) becomes (roughly) proportional to the base current (Ib). The amount of current flowing into the collector vs that into the base (Ic/Ib) is roughly the transistor beta which is specific to the device and doesn't radically change for a certain specified range of operating parameters which includes Vce (although it will change depending on certain conditions). As such, you can estimate collector current via Ic=Ib * Beta in a test setup (note that beta is rarely used in this specific fashion for actual design purposes).
Okay,Thank you for the answer...
But Let's go a little bit in physics class...
How can I know the co-ordinates of knee points and the equation of the blue line?
so I can bias (in theoretical way) correctly
one more question....I see how the load line intercept the blue line there so Is that the maximum Ib and Ic that I can get in SAT mode? and what's gonna happen if I continue to increase my Ib?
The blue line is reasonably Vce(sat) and depends on the device; each will have a different value. For many small signal devices Vce(sat) is typically under 300 mV, but could be significantly different and you can get this from the data sheets.
Ib has an effect on Vce indirectly through Ic. Given a finite Vcc and (relatively) fixed Vce(sat); at some point increasing Ib will not be able to pull Vce below the Vce(sat); there is also an intrinsic resistance which (without a load resistor) limits current regardless of Ib (you never get more current than (Vcc-Vce(sat))/Rce(sat)); eventually you'll just burn out the device.
You don't bias this way (correctly); you generally bias by setting an appropriate operating point with a reasonable margin from Vce(sat) somewhere in the active region.