Hi there - I'm working on the layout of a PCB that will be carrying
~30A or so. I'm running some parallel traces to increase the current
carrying capacity of the PCB. I would like these traces to be
connected with vias. My question is this: Is it better to have lots of
really small vias, or just a few really large vias? Also, should these
traces be connected just at either end of the trace, or should they
have vias connecting them throughout the trace?
You can do relately simple resistance estimations on printed wiring
Copper Resistance: Rc= r . L/HW
r = 1.7241WcmE-6 or 6.786WinE-7
Tempco Tc= +.039%/°C
R = K L/W
K @ 1oz (H=.0014 or .035mm) = 4.84E-4
@ 2oz (H=.0028 or .070mm) = 2.43E-4
@ 3oz (H=.0042 or .105mm) = 1.61E-4
@ 4oz (H=.0056 or .140mm) = 1.21E-4
@ foil .01 = 6.79E-5
@ foil .02 = 3.39E-5
@ foil .05 = 1.37E-5
@ bar .10 = 6.8E-6
Note: K is traditionally expressed as ohms/square,
as L/W of the 'printed' square is 1.
The resistivity of 1oz copper can therefore be considered as 0.48
L/W 2oz 3oz 4oz
1 .243 .16 .121 mohms
10 2.43 1.61 1.21 mohms
100 24.3 16.1 12.1 mohms
- and a 1oz Plated-Through-Hole .062L .0017H
dia. 0.02 W=0.0613 R=0.48mohms
dia. 0.04 W=0.1257 R=0.24mohms
dia. 0.06 W=0.1885 R=0.159mohms
neglecting solder fill.
Individual squares (with individual L/W ratios) along the length of a
complicated trace-width are simply additive, like series resistors
would be. Parallel traces can be treated as parallel resistors.
Self-heating of the trace and the surface temperatue rise resulting,
in free air, can still be first order approximated as 1deg rise for
every mW dissipated from a cm^2 surface area.
So depending on what you're trying to do, there's no reason why you
shouldn't be able to check for effectiveness, potential hotspots,
efficiency effects and overkill.