Second Stage of Op-Am (Current to Voltage)

[Dan Dunphy]

Top posted.
In a DC analysis, the capacitor has no function, you could look at it
as sinking or sourcing current in a transient analiysis, or in AC it
is simply miller effect throwing in a low frequency pole, as you said.
This guarantees stability at a gain of one, without external
compensation.
The mirror never pulls current out of the base of the second stage, it
just steals the base drive, supplied by the trasistor in the diff amp,
above, depending on how the input amp is tipped. Can't read your
diagram.

It says I don't have permission to access the link posted.

Looking at it open loop is meaningless in the practical sense, it
could theoretically balance the output, but the Gain A is probably
100K minimum, at DC. In the real world, it act like a slow comparitor
with no hysteresis. The max slew rate is limited by the miller
capacitor mentioned above.

There should be a pullup on the second stage collector, either a
resistor or a current source to Vcc
Dan

 

[Active8]

First off, look at the piss poorly posed questions in my other
subthread with the OP. He gave Ic1 - Ic2 = Iout negative as the
condition, and wants to know where the negative Iout is going to
come from - then my answer is that it ain't. For all I know
Intuitive ICs for Telemarketers would've skipped the initial
condidtion of the cap prior to that state, so forget that. I
couldn't assume that on page x where he's still blabbering about a
DC condition like Ic1 - Ic2 = Iout, that he's also talking about a
steady state condition where Cc *might* be obliging and supply some
reverse Iout.

So where's the AC generator anyway? None drawn nor mentioned.

So, you believe that Q4 cannot conduct at a lower
Vce than that? How do you think saturated BJT's work?

Q4 can't go below Vee (+ Vce_sat) and that's what the emitter of
Qmiller is connected to. If you *could* go below Vee to *try* to
draw current from Qmiller, Qmiller would be reversed biased.

If the Qnameless/Cc combo provided only a single pole,
calling "a pole, nothing more" would be fine, I guess. My
point is simply that it has more effect in applications where
closed loop stability becomes an issue.
Yup.



I do and did see it. It is a minor term.

Bull! It's a gain limiting term.

In that state, Q2 and Q4 collector currents are nearling balanced.
To say the output comes from one only is oversimplified. Once
at that state, if Vo begins to move positive at a rate faster
than Ib(Qnameless)/Cc, net current at Vo' will be leaving
to the left. According to your way of thinking, it would be
going to Q4.

That's differen't from what the OP was asking (look at the OP) and
as I said, it's an effect of Cc - that may or may not manifest, BTW,
like you said. You mean slewing. That's not the same as the
condition given i.e., Ic1 - Ic2 = Iout negative.

 

[Dan Dunphy]

Top post

Multiple emitters is common practice. Virtually all TTL inputs are
done that way.
In an epitaxial process, One simply diffuses 1 to n emitters into the
base region, of the NPN input transistor, and connect them to the
outside world.
The active input state, per emitter is is low.

Dan

 

[Larry Brasfield]

Bull! It's a gain limiting term.

Let's see ... You have Ro_Q4 in parallel with Ri_Qmiller.
Ri_Qmiller is going to be in the neighborhood of
Beta * (Vt / Io)
whereas ro_Q4 will be something like
Vearly / Ic1
So, for Ri_Qmiller to be comparable to Ro_Q4, (and taking
Io to be similar to Ic1, an assumption generous to you), we
need to have Beta * Vt =~ Vearly or Beta =~ Vearly / Vt.
Typical values of Vearly are 40, and Vt is about 26 mV,
so you need Beta near 1500 in order to keep the Q4
impedance term from becoming minor. It gets worse with
a more reasonable assumption about Io relative to Ic1.

Perhaps you have overlooked the fact that the smaller
impedances dominate in a parallel connection.

That's differen't from what the OP was asking (look at the OP) and
as I said, it's an effect of Cc - that may or may not manifest, BTW,
like you said. You mean slewing. That's not the same as the
condition given i.e., Ic1 - Ic2 = Iout negative.

Do you believe that Ic1 can never exceed Ic2? If so,
what do you suppose happens if (Vin(+) - Vin(-))
is more positive than, say, a few 10's of mV?
If not, why can't you see that since Iout is defined
as Ic2-Ic1, that expression can become negative?
And please, no jabber about the steady state. We
are adressing your proposition, and I quote: "I told
you Iout can't be negative" and "I used to believe
that the current would flow bidirectionally".

This is getting a bit wearying, so I may not respond further.

 

[Active8]

Let's see ... You have Ro_Q4 in parallel with Ri_Qmiller.
Ri_Qmiller is going to be in the neighborhood of
Beta * (Vt / Io)
whereas ro_Q4 will be something like
Vearly / Ic1
So, for Ri_Qmiller to be comparable to Ro_Q4, (and taking
Io to be similar to Ic1, an assumption generous to you), we
need to have Beta * Vt =~ Vearly or Beta =~ Vearly / Vt.
Typical values of Vearly are 40, and Vt is about 26 mV,
so you need Beta near 1500 in order to keep the Q4
impedance term from becoming minor. It gets worse with
a more reasonable assumption about Io relative to Ic1.

Perhaps you have overlooked the fact that the smaller
impedances dominate in a parallel connection.

Nope and if you were following the threads, you'd know that the
circuit OP linked to has a follower *and* a CE stage for the miller
stage with a 100 ohm resistor on the emitter of the CE stage. So if
beta were 100 that's Rin of 1 Meg. Sorry, I never shifted gears back
to the figure below. Big difference.

Do you believe that Ic1 can never exceed Ic2? If so,
what do you suppose happens if (Vin(+) - Vin(-))
is more positive than, say, a few 10's of mV?
If not, why can't you see that since Iout is defined
as Ic2-Ic1, that expression can become negative?

So what the expression can be negative? Leave it there until the cap
is done discharging and tell me where the current will come from.

And please, no jabber about the steady state. We
are adressing your proposition, and I quote: "I told
you Iout can't be negative" and "I used to believe
that the current would flow bidirectionally".

I still do as long as we're not trying to get bidirectional flow
from the base of a bjt. If the cap (even the b-c cap) pumps current
that way sometimes, that's a transient response. After that, the
diff stage can ask for as much as it wants and if it could go below
the rail, it'd keep doing so until the b-e breaks down in reverse.

 

[Monty Hall]

I used to believe that the current would flow bidirectionally 'till

I told you Iout can't be negative before I pulled that circuit.
Don't be an ass. You'd probably save time and frustration if you
*did* take the time to do this in Spice. It's much easier to see the
currents and why they're not what you expected.


I told you. The circuit can never do this. Vo' is pinned at 1 Vbe
above Vee. If you drove Vin(+) so high that it cuts off, Q4 will try
to get that current from the next stage and it can't. Q4's collector
will drop below the Vbe (head for the lower rail) of the 2nd stage
and the 2nd stage will be in cutoff as a result. Replace the 2nd
stage with a resistor connected to (Vcc - Vee)/2 or if you want that
bidirectional behavior.

I've updated the schematic to give the nameless transistor a name. Qout's
emitter is grounded w/ intrisic resistance of ~X/Ic plus the output
collector voltage is being balanced with current source to achieve the high
VOLTAGE gain(see below about active loads). The base voltage is determined
by the differential amplifier current mirror active load so Vo' is not
pinned. Your naive application of a diode drop is no longer relevant and
for the most part not used in much of the core design - except the output
stage and support circuity. We're in Ebers-Moll/Mextram land now. Plot Vo'
on SPICE - it's not pinned and is determined by the differential amplifier
not (ground + Qout's Vbe). You could argue what you really meant is that
Vbe is pinned indirectly calculated by the differential input stage. You're
not that clever and your causality is screwed up. Qout is a high input
impedance and high gain stage. Please skip the tangent on poles...

Was that articulate enough?

No.

What part of analytical don't you understand? Found my answer that explains
the relationship between the op-amp's stage 1 & 2 rather well,
http://users.ece.gatech.edu/~mleach/ece4435/tutorial.pdf. Possibly here,
http://www.national.com/an/AN/AN-A.pdf, but I've only briefly looked @ it.
You've actually been helpful for once. You're magic SPICE demo prompted me
to get a free SPICE simulator - not that I'm fond of simulators. See
circuit below.

Rails, saturation, poles, version of 741, etc, relevant to the derivation?
I don't think so. If you read my other posts, I ultimately wanted to get a
derived transfer function so I could see - though the process of
derivation - the interplay between stages 1 & 2. I also asked if (V+ - Vi)
was transduced to 1.) high impedance voltage source or 2.) bi-directional
current source. All that other pedantic BS you were talking about - wasting
other's time - can be analyzed/factored later.

In Frederickson's "Intuitive IC Op Amps", I was taking him @ face value that
Iout = Ic2 - Ic1 ie: Iout can be made up externally & be bi-directional.
This is what your learn in DC analysis of two differing current sources
flowing in series & an output line - the delta is made up through a load on
the output line(as long collectors are in linear active region). Since this
is where the Iout controversy exists - I needed to reevaluate how the stage
1 - differential amp w/ current mirror active load works(DACMAL).

It's true that if the load impedance on Iout is "just right", the collectors
Q2 & Q4 are in the active region & Iout = Ic2 - Ic1 is true and so is the
possibility of its bi-directionality. However, where I went wrong is that I
ignored output impedance @ Iout. It's absolutely not "just right". It's
actually very large and the current is unidirectional. In this
configuration, the transduction of (V+ - V-) isn't to current- ie: Iout -
but rather voltage something like Vo' = A(V+ - V-). Horowitz & Hill in the
"Art of Electronics" said the output impedance of the DACAML must be high -
and treated it as a voltage source output not current. They also mention
the gain of this configuration to be 5000+ (early 80's text).

Using SPICE, if one input is grounded and the other input allowed to sine
oscillate the output voltage Vo' is virtually a square wave under transient
analysis. If the input is made small enough, the output is replicated &
scaled by virtue of operating in the square's transistion region. The
phenomena being manipulated in the DACAML is the transistors' balancing of
collector voltages(between saturation) of Q2 & Q4 to try and make up
unobtainable collector current deltas. The modelling goes beyond using
simple constant value transistor diode drops and beta.

Looking @ Leach's analysis, negative Iout(V+ - Vi) can exist
(differentially - not absolutely - by superposition) wrt to the capacitor
and that Qout serves as a high input impedance voltage gain. Removing the
cap from the SPICE simulation still works(as you claimed) - though impacting
AC performance. Again in an ac small signal sense, it's not really
incorrect to view stage 1 as tranduction of V+ - Vi to current Iout - as
Fredericken claims.

As a layperson - trying to learn how the basic op-amp works internally - I
missed his point and took it literally in DC - but it seems to have eluded
you as well.

Regards my Argumentative Jargon Laiden Lad,


Monty



+Vcc +Vcc
o o
| |
| |
2 Ic = Bias Current Io = Bias Current
| |
| |
| |
o------o-----o |
| | |
|< >| o-------o----o Vo
Vin(-) -| Q1 Q2 |- Vin(+) | |
|\ /| Cc --- o
|Ic1 Ic2 | --- |
| | Vo' | |/
| o----------------------o---o-| Qout
| | Iout |>
| | o
| | |
| | Ic1 |
| o |
| |/ |
o----o---o-| Q4 |
| | |> |
| | Ic1 o |
| o | |
| |/ | |
|--| Q3 | |
|> | |
| | |
-------o |
| |
| |
-Vee -Vee
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

 

[Monty Hall]

I need to make a correction it is (-Vee + Qout's Vbe) not (ground + Qout's
Vbe). Damn split power supplies. Change is included along w/ few mods.

Monty

===============================

I told you Iout can't be negative before I pulled that circuit.
Don't be an ass. You'd probably save time and frustration if you
*did* take the time to do this in Spice. It's much easier to see the
currents and why they're not what you expected.


I told you. The circuit can never do this. Vo' is pinned at 1 Vbe
above Vee. If you drove Vin(+) so high that it cuts off, Q4 will try
to get that current from the next stage and it can't. Q4's collector
will drop below the Vbe (head for the lower rail) of the 2nd stage
and the 2nd stage will be in cutoff as a result. Replace the 2nd
stage with a resistor connected to (Vcc - Vee)/2 or if you want that
bidirectional behavior.

I've updated the schematic to give the nameless transistor a name. Qout's
emitter is grounded w/ intrisic resistance of ~X/Ic plus the output
collector voltage is being balanced with current source to achieve the high
VOLTAGE gain(see below about active loads). The base voltage is determined
by the differential amplifier current mirror active load so Vo' is not
pinned. Your naive application of a diode drop is no longer relevant and
for the most part not used in much of the core design - except the output
stage and support circuity. We're in Ebers-Moll/Mextram land now. Plot Vo'
on SPICE - it's not pinned and is determined by the differential amplifier
not (-Vee + Qout's Vbe). You could argue what you really meant is that
Vbe indirectly influenced by the differential input stage. You're
not that clever and your causality is screwed up. Qout is a high input
impedance and high gain stage. Please skip the tangent on poles...

Was that articulate enough?

No.

What part of analytical don't you understand? Found my answer that explains
the relationship between the op-amp's stage 1 & 2 rather well,
http://users.ece.gatech.edu/~mleach/ece4435/tutorial.pdf. Possibly here,
http://www.national.com/an/AN/AN-A.pdf, but I've only briefly looked @ it.
You've actually been helpful for once. You're magic SPICE demo prompted me
to get a free SPICE simulator - not that I'm fond of simulators. See
circuit below.

Rails, saturation, poles, version of 741, etc, relevant to the derivation?
I don't think so. If you read my other posts, I ultimately wanted to get a
derived transfer function so I could see - though the process of
derivation - the interplay between stages 1 & 2. I also asked if (V+ - Vi)
was transduced to 1.) high impedance voltage source or 2.) bi-directional
current source. All that other pedantic BS you were talking about - wasting
other's time - can be analyzed/factored later.

In Frederickson's "Intuitive IC Op Amps", I was taking him @ face value that
Iout = Ic2 - Ic1 ie: Iout can be made up externally & be bi-directional.
This is what your learn in DC analysis of two differing current sources
flowing in series & an output line - the delta is made up through a load on
the output line(as long collectors are in linear active region). Since this
is where the Iout controversy exists - I needed to reevaluate how the stage
1 - differential amp w/ current mirror active load works(DACMAL).

It's true that if the load impedance on Iout is "just right", the collectors
Q2 & Q4 are in the active region & Iout = Ic2 - Ic1 is true and so is the
possibility of its bi-directionality. However, where I went wrong is that I
ignored output impedance @ Iout. It's absolutely not "just right". It's
actually very large and the current is unidirectional. In this
configuration, the transduction of (V+ - V-) isn't to current- ie: Iout -
but rather voltage something like Vo' = A(V+ - V-). Horowitz & Hill in the
"Art of Electronics" said the output impedance of the DACAML must be high -
and treated it as a voltage source output not current. They also mention
the gain of this configuration to be 5000+ (early 80's text).

Using SPICE, if one input is grounded and the other input allowed to sine
oscillate the output voltage Vo' is virtually a square wave under transient
analysis. If the input is made small enough, the output is replicated &
scaled by virtue of operating in the square's transistion region. The
phenomena being manipulated in the DACAML(or it seems collector active
loads) is
the transistors' balancing of collector voltages(between saturation) of Q2 &
Q4
to try and make up unobtainable collector current deltas resulting in a high
impedance voltage gain. The modelling goes beyond using simple constant
value
transistor diode drops and beta.

Looking @ Leach's analysis, negative Iout(V+ - Vi) can exist
(differentially - not absolutely - by superposition) wrt to the capacitor
and that Qout serves as a high input impedance voltage gain. Removing the
cap from the SPICE simulation still works(as you claimed) - though impacting
AC performance. Again in an ac small signal sense, it's not really
incorrect to view stage 1 as tranduction of V+ - Vi to current Iout - as
Fredericken claims.

As a layperson - trying to learn how the basic op-amp works internally - I
missed his point and took it literally in DC - but it seems to have eluded
you as well.

Regards my Argumentative Jargon Laiden Lad,


Monty



+Vcc +Vcc
o o
| |
| |
2 Ic = Bias Current Io = Bias Current
| |
| |
| |
o------o-----o |
| | |
|< >| o-------o----o Vo
Vin(-) -| Q1 Q2 |- Vin(+) | |
|\ /| Cc --- o
|Ic1 Ic2 | --- |
| | Vo' | |/
| o----------------------o---o-| Qout
| | Iout |>
| | o
| | |
| | Ic1 |
| o |
| |/ |
o----o---o-| Q4 |
| | |> |
| | Ic1 o |
| o | |
| |/ | |
|--| Q3 | |
|> | |
| | |
-------o |
| |
| |
-Vee -Vee
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)