I need to make a correction it is (-Vee + Qout's Vbe) not (ground + Qout's
Vbe). Damn split power supplies. Change is included along w/ few mods.
Monty
===============================
I told you Iout can't be negative before I pulled that circuit.
Don't be an ass. You'd probably save time and frustration if you
*did* take the time to do this in Spice. It's much easier to see the
currents and why they're not what you expected.
I told you. The circuit can never do this. Vo' is pinned at 1 Vbe
above Vee. If you drove Vin(+) so high that it cuts off, Q4 will try
to get that current from the next stage and it can't. Q4's collector
will drop below the Vbe (head for the lower rail) of the 2nd stage
and the 2nd stage will be in cutoff as a result. Replace the 2nd
stage with a resistor connected to (Vcc - Vee)/2 or if you want that
bidirectional behavior.
I've updated the schematic to give the nameless transistor a name. Qout's
emitter is grounded w/ intrisic resistance of ~X/Ic plus the output
collector voltage is being balanced with current source to achieve the high
VOLTAGE gain(see below about active loads). The base voltage is determined
by the differential amplifier current mirror active load so Vo' is not
pinned. Your naive application of a diode drop is no longer relevant and
for the most part not used in much of the core design - except the output
stage and support circuity. We're in Ebers-Moll/Mextram land now. Plot Vo'
on SPICE - it's not pinned and is determined by the differential amplifier
not (-Vee + Qout's Vbe). You could argue what you really meant is that
Vbe indirectly influenced by the differential input stage. You're
not that clever and your causality is screwed up. Qout is a high input
impedance and high gain stage. Please skip the tangent on poles...
Was that articulate enough?
No.
What part of analytical don't you understand? Found my answer that explains
the relationship between the op-amp's stage 1 & 2 rather well,
http://users.ece.gatech.edu/~mleach/ece4435/tutorial.pdf. Possibly here,
http://www.national.com/an/AN/AN-A.pdf, but I've only briefly looked @ it.
You've actually been helpful for once. You're magic SPICE demo prompted me
to get a free SPICE simulator - not that I'm fond of simulators. See
circuit below.
Rails, saturation, poles, version of 741, etc, relevant to the derivation?
I don't think so. If you read my other posts, I ultimately wanted to get a
derived transfer function so I could see - though the process of
derivation - the interplay between stages 1 & 2. I also asked if (V+ - Vi)
was transduced to 1.) high impedance voltage source or 2.) bi-directional
current source. All that other pedantic BS you were talking about - wasting
other's time - can be analyzed/factored later.
In Frederickson's "Intuitive IC Op Amps", I was taking him @ face value that
Iout = Ic2 - Ic1 ie: Iout can be made up externally & be bi-directional.
This is what your learn in DC analysis of two differing current sources
flowing in series & an output line - the delta is made up through a load on
the output line(as long collectors are in linear active region). Since this
is where the Iout controversy exists - I needed to reevaluate how the stage
1 - differential amp w/ current mirror active load works(DACMAL).
It's true that if the load impedance on Iout is "just right", the collectors
Q2 & Q4 are in the active region & Iout = Ic2 - Ic1 is true and so is the
possibility of its bi-directionality. However, where I went wrong is that I
ignored output impedance @ Iout. It's absolutely not "just right". It's
actually very large and the current is unidirectional. In this
configuration, the transduction of (V+ - V-) isn't to current- ie: Iout -
but rather voltage something like Vo' = A(V+ - V-). Horowitz & Hill in the
"Art of Electronics" said the output impedance of the DACAML must be high -
and treated it as a voltage source output not current. They also mention
the gain of this configuration to be 5000+ (early 80's text).
Using SPICE, if one input is grounded and the other input allowed to sine
oscillate the output voltage Vo' is virtually a square wave under transient
analysis. If the input is made small enough, the output is replicated &
scaled by virtue of operating in the square's transistion region. The
phenomena being manipulated in the DACAML(or it seems collector active
loads) is
the transistors' balancing of collector voltages(between saturation) of Q2 &
Q4
to try and make up unobtainable collector current deltas resulting in a high
impedance voltage gain. The modelling goes beyond using simple constant
value
transistor diode drops and beta.
Looking @ Leach's analysis, negative Iout(V+ - Vi) can exist
(differentially - not absolutely - by superposition) wrt to the capacitor
and that Qout serves as a high input impedance voltage gain. Removing the
cap from the SPICE simulation still works(as you claimed) - though impacting
AC performance. Again in an ac small signal sense, it's not really
incorrect to view stage 1 as tranduction of V+ - Vi to current Iout - as
Fredericken claims.
As a layperson - trying to learn how the basic op-amp works internally - I
missed his point and took it literally in DC - but it seems to have eluded
you as well.
Regards my Argumentative Jargon Laiden Lad,
Monty
+Vcc +Vcc
o o
| |
| |
2 Ic = Bias Current Io = Bias Current
| |
| |
| |
o------o-----o |
| | |
|< >| o-------o----o Vo
Vin(-) -| Q1 Q2 |- Vin(+) | |
|\ /| Cc --- o
|Ic1 Ic2 | --- |
| | Vo' | |/
| o----------------------o---o-| Qout
| | Iout |>
| | o
| | |
| | Ic1 |
| o |
| |/ |
o----o---o-| Q4 |
| | |> |
| | Ic1 o |
| o | |
| |/ | |
|--| Q3 | |
|> | |
| | |
-------o |
| |
| |
-Vee -Vee
(created by AACircuit v1.28.4 beta 13/12/04
www.tech-chat.de)