Semiconductor fabrication question

[linnix]

Out of curiosity, what do you think annealing does?

Turning the top layer as well as the substrate (through a metal layer)
into polysilicon. How do you propose to stop the substrate from 1000C
through the metal layer?

 

[linnix]

Sorry? What does that mean?

Cheers,

Phil Hobbs

He is putting a thin layer of silicon on metal on silicon and hoping
to get polysilicon on metal on silicon. I am just saying that he will
get polysilicon on metal on polysilicon.

 

[[email protected]]

Annealing won't turn single-crystal silicon into poly.  Single-crystal
boules are pulled from melt--which is quite a bit hotter than anybody's
anneal.  The longer you anneal, the larger the crystals become.

A more pertinent point would be whether the metal is refractory enough
not to diffuse into the silicon.  Some will, some won't.

Cheers.

Phil Hobbs- Hide quoted text -

Great point! I was concerned about the metal and semiconductor
diffusing. The only refractory metal I'm aware of is Tungsten.

Thanks,
Anon

 

[[email protected]]

Here's a picture of my first goal

http://sites.google.com/site/curiousjohn4/

Note, in the final product, the green (deposited doped silicon) should
be poly-silicon, not amorphous silicon.

Here's a thought, not sure how true. It's difficult to say the
mobility of a material since it varies so much depending on a lot of
details. Amorphous silicon mobility can range from 0.5 to a few dozen
m^2/Vs, and polysilicon at 1000cm^2/Vs. A heavy doped semiconductor
has more majority carriers, so it seems to me it will have higher
mobility. I read that typically lower bandgap materials tend to have
higher mobility and higher bw. So it sounds like higher doped
materials tend (perhaps not always) to have higher bw. On top of that,
the depletion width decreases relative to the sqrt(N) where N is the
dopant density in the schottky diode, so heavy doped means smaller
depletion width. A smaller depletion width should mean lower transit
times, which would mean a faster responding diode, at least faster
through the depletion region.

Anon

 

[[email protected]]

Here's a thought, not sure how true. It's difficult to say the
mobility of a material since it varies so much depending on a lot of
details. Amorphous silicon mobility can range from 0.5 to a few dozen
m^2/Vs, and polysilicon at 1000cm^2/Vs. A heavy doped semiconductor
has more majority carriers, so it seems to me it will have higher
mobility. I read that typically lower bandgap materials tend to have
higher mobility and higher bw. So it sounds like higher doped
materials tend (perhaps not always) to have higher bw. On top of that,
the depletion width decreases relative to the sqrt(N) where N is the
dopant density in the schottky diode, so heavy doped means smaller
depletion width. A smaller depletion width should mean lower transit
times, which would mean a faster responding diode, at least faster
through the depletion region.

Anon

Sorry I made a mistake. The mobility decreases when the dopant density
increase. Darn!

Anon

 

[przemek klosowski]

Nonsense. Rapid thermal anneals of 900-1100C are common.

And you don't think it will anneal everything explosed?[/QUOTE]

The crystalline structure has the lowest energy and given enough
time or energetic activation (i.e. heating) will be the ultimate
configuration. Polycrystalline silicon has slightly higher energy, and
amorphous is much higher. There are energy barriers between those
states, though, so it's possible to 'quench' into a higher energy
state. The speed with which the system relaxes into the lowest
energy configuration is exponential with temperature (~ exp(-kT/dE)
so if the temperature is much below the energy difference between
the states divided by Boltzmann constant k, the configuration is
practically stable (frozen), even if it is not the globally lowest
energy state.

The same principle governs the diffusion processes that destroy
the doping gradients that make the semiconductor structures, of
course, and that's why high T kills the devices. What matters here
is the relative speed of all those diffusion and relaxation processes.
If you control the amount and profile of the heat impulse, you may
be able to get enough of the desired change, without causing
too much of the damage.

 

[[email protected]]

Out of curiosity, what do you think annealing does?

Cheers,

Phil Hobbs- Hide quoted text -

- Show quoted text -

Annealing allows the amorphous silicon to crystallize. Having
answered the question I thought it OK to make my own 'ignorant'
observation/ question. The OP was proposing to evaporate doped Si.
As I understood it he was going to purchase a doped Si wafer, put it
in an oven and evaporate it onto something else. I wondered if the
dopant atoms would boil at the same temperature as the Si? Would they
leave first, be carried along in the 'stream', or pool on the surface?

Hey how 'bout laser ablation.

George Herold

 

[Rich Grise]

.

Annealing allows the amorphous silicon to crystallize. Having answered
the question I thought it OK to make my own 'ignorant' observation/
question. The OP was proposing to evaporate doped Si. As I understood it
he was going to purchase a doped Si wafer, put it in an oven and evaporate
it onto something else. I wondered if the dopant atoms would boil at the
same temperature as the Si? Would they leave first, be carried along in
the 'stream', or pool on the surface?

Hey how 'bout laser ablation.

You could sputter it (ionic ablation).

Cheers!
Rich

 

[JosephKK]

The reason for asking is Phil Hobbs said that sputtered silicon on a
PCB would result in a layer of amorphous silicon. I want the deposited
layer to be doped polysilicon, not doped amorphous silicon. So what if
I replace the PCB with an undoped polysilicon wafer? Actually I drew
an example of what I want to do. In the following image, lets say the
deposited method was to heat a piece of metal inside a vacuum, which
would slowly cause some of the heated atoms to fly on the wafer, and
next I would use the same method except it would be heated dopded
silicon instead of heated metal. This would result in a layer of metal
on the wafer followed by a layer of silicon (hopefully polysilicon).

http://sites.google.com/site/curiousjohn4/

Thanks,
Anon

To tell the truth, i am not so sure. IIRC if you use a sputtering
process you get mostly amorphous Si, but that is convertible into
majority polysilicon by annealing. Most vapor phase depositions tend
toward crystalline forms, but they are slower.

 

[JosephKK]

Thanks for the info Phil! Slowly, but surely, I'll get it right. I
was told CVD is too dangerous for a garage operation. Wouldn't even
know where to buy the silane, and would be afraid to handle it. One
leak and kaboom!

The annealing step after depositing amorphous Si sounds hopeful for a
garage project. I'll start reading up on that semiconductor annealing
process, but haven't read about it yet. Sounds like some hope.

May I ask is GaAs easier to get in the crystal form?

Thanks,
Anon

More difficult to obtain and much more expensive. Also much more
expensive to process.

Just the same you may peruse the following if you are interested in
diffusion or epitaxy:

http://encyclopedia.airliquide.com/Encyclopedia.asp?GasID=57
http://msds.chem.ox.ac.uk/AR/arsine.html

and here

http://www.voltaix.com/msds.htm

Joseph

 

[JosephKK]

I found the wikipage

http://en.wikipedia.org/wiki/Furnace_anneal

Lets say the junction plate width is are around 1um diameter, the
depletion width is very thin at 10nm for heavy doped Schottky, and
they are baked in the furnace at 550C to convert the amorphous silicon
to polysilicon. Any drawbacks to that process, perhaps enough metal-
semiconductor atoms diffusing to result in poor performance?


Thanks for any help and advice,
Anon

Diffusion is both temperature and time dependant, not to mention
whether or not the diffusion source is in contact with the object
material. Most diffusion ovens operate above 650 C and provide
continuous dopant supply. There are equations for the solid
solubility and diffusion rates if you look for them.

 

[JosephKK]

Thanks. I'm a bit confused why Phil H. would say that I could anneal
the chip to convert from amorphous-silicon to poly-silicon if it would
destroy the chips properties.

It was said that CVD is too dangerous for a garage project. Are there
any other options we have not explored? What about solid-phase
crystallization (SPC), or perhaps metal-induced crystallization?

Thanks,
Anon

I think ion implantation may be garage shop doable. Not in the least
easy mind you, see the MSDS for the source dopants.

 

[JosephKK]

Here's a picture of my first goal

http://sites.google.com/site/curiousjohn4/

Note, in the final product, the green (deposited doped silicon) should
be poly-silicon, not amorphous silicon.

Thanks,
Anon

CVD is probably too hazardous for urban / suburban garage shop, but
then so is diffusion ovens. If the nearest neighbor is at least 1
mile away most anything can be acceptable, but not MIC.

 

[JosephKK]

No semiconductor structure can withstand 500 degree annealing
temperature. In real life, polysilicon is annealed first, then
implanted into structures. You need the proper equipment and site to
do it. They (the fab houses) usually spend several hundred millions
dollars for them.

ERROR! MUST STERILIZE!

There is no such process as implanting polysilicon, it must be
deposited. Or amorphous silicon deposited and converted to
polysilicon by annealing.

 

[JosephKK]

[snip]

Perhaps I misunderstood what you are trying to do and how you are
doing it.

Here's a picture of my first goal

Note, in the final product, the green (deposited doped silicon) should
be poly-silicon, not amorphous silicon.

Thanks,
Anon

No semiconductor structure can withstand 500 degree annealing
temperature. In real life, polysilicon is annealed first, then
implanted into structures. You need the proper equipment and site to
do it. They (the fab houses) usually spend several hundred millions
dollars for them.

I've made a lot of instruments that cost me practically nothing that
would have cost a furtune to buy. In this case I don't need fancy
equipment that's good for mass producing chips. So if it takes a week
per chip, then whatever.

I'm reading that if the amorphous silicon is on metal then it requires
far less temperature to convert it from amorphous to poly. Yesterday I
read that 150C is enough. I know most semiconductor components can
stand at least 220C. I don't know how thick the metal needs to be
though.

Another option, perhaps there's another method to deposit poly-silicon
other than CVD that is safe.


Anon

I got to thinking a bit sideways on this. You can probably achieve
almost all the methods involved in early semiconductor processing
(this will take you up through early ion implantation techniques) if
you partner with a local high school or college. All of them are
still in use.

 

[JosephKK]

As I told Phil Hobbs, the chunk of silicon that is to be heated up for
evaporation method is poly-silicon. I don't think that makes much
difference.


Why would CVD deposit poly-silicon on the surface, while evaporation
methods would deposit amorphous silicon? Perhaps if the evaporation
method was kept at an extremely low rate. Perhaps by lowering the
evaporation temperature. Of course lowering the evaporation
temperature would increase the time required to deposit the silicon.

Thanks for any help,
Anon

It is not so much what the material you convert to vapor but the
nature of the solid condensation process that determines the outcome.

 

[JosephKK]

Here is something describing the silicon junction breakdown at around
200C to 300C. I did not read the detail, but I think it is in the
right ball park figure.

http://adsabs.harvard.edu/abs/1969JaJAP...8..917O

1969, mesa devices, that is pretty out of date.

 

[JosephKK]

You know, it may be possible that a low temp below 200C annealing
process done for a very long time could work over and over might
convert the amorphous to polysilicon. It may not be mentioned in the
industry because it would be impractical, too slow, but I have plenty
of time. In this case the silicon is on top of metal, so that also
helps.

Thanks,
Anon

Not necessarily. You must also consider the crystal pitch (atomic
spacing in the crystalline form). If the substrate pitch in not very
similar to what you want to deposit, you get seriously many crystal
lattice imperfections. And if tempco of expansion is dissimilar,
trouble results from thermal cycling.

 

[JosephKK]

My factory needs 10 to 15 weeks for CVD of a 15um device with 4
masks. How slow do you want to do yours, even if it makes any
difference.

Sounds like a scheduling issue. Tough luck.

 

[JosephKK]

Great point! I was concerned about the metal and semiconductor
diffusing. The only refractory metal I'm aware of is Tungsten.

Thanks,
Anon

Try this:

http://en.wikipedia.org/wiki/Refractory_metal

also various elements by melting point:

http://en.wikipedia.org/wiki/List_of_elements_by_melting_point

Not perfect nor complete.