# Simple digital pulse delay,..

N

#### [email protected]

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

N

#### [email protected]

Jan 1, 1970
0
On 14 May, 08:24, [email protected] wrote:
...
However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF i

....should have been 74HC74

D

#### David L. Jones

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

How accurate does the delay need to be?
IRCC a 4000 series CMOS gate has a typical 5V propagation delay of around
100ns. So stringing 4 or 5 of those in series will get you close to what you
want. Will vary with temp and voltage rail of course, but might be good

Dave.

D

#### David L. Jones

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

How accurate does the delay need to be?
IRCC a 4000 series CMOS gate has a typical 5V propagation delay of around
100ns. So stringing 4 or 5 of those in series will get you close to what you
want. Will vary with temp and voltage rail of course, but might be good

Dave.

N

#### [email protected]

Jan 1, 1970
0
How accurate does the delay need to be?
IRCC a 4000 series CMOS gate has a typical 5V propagation delay of around
100ns. So stringing 4 or 5 of those in series will get you close to what you
want. Will vary with temp and voltage rail of course, but might be good

Not very accurate at all - it's a safety zone and, in this app, not
particularly mission critical (except it might stop the bridge self-
destructing).

The bridge has been perfectly happy so far without dead-time, but I
would prefer a bit of safety as there are high currents & voltages
around...

Thanks for the input

B

#### [email protected]

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

You can get 500nsec out of a monostable. The 74121 and 221 can get
down to 70nsec

http://www.datasheetcatalog.org/datasheet/philips/74HC_HCT221_CNV_2.pdf

There are lots of other monostables around. The last time I had to set
set up a roughly 50nsec delay, which was fine for the MOSFET switches
I was using.

P

#### Pete Wilcox

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...
If you've got a couple of spare buffers or inverters somewhere on your cct
board, feed your signal into one then connect its output to the second one
via a resistor, with a small capacitance between the second buffer's input
and ground. For a delay of 500nS, values of 100 ohms and 4.7nF should do
the job nicely.

Cheers,
Pete.

M

#### MooseFET

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

S

#### Spehro Pefhany

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

You want to insert asymmetrical delays into both the high and low side
switching signals (Fast off, slow on).

For example (view in fixed width font only)

Active HIGH input 1/2 74HC132
__ __
o----+----------| \ +-| \
| ___ | )o---+ | )o-o HIGH SIDE
+--|___|-+-|__/ +-|__/
|
4K7 ---
--- 100pF
|
|
===
GND

Active HIGH input 1/2 74HC132
__ __
o----+----------| \ +-| \
| ___ | )o---+ | )o-o LOW SIDE
+--|___|-+-|__/ +-|__/
|
4K7 ---
--- 100pF
|
|
===
GND

P

#### Pete Wilcox

Jan 1, 1970
0
For example (view in fixed width font only)

Active HIGH input 1/2 74HC132
__ __
o----+----------| \ +-| \
| ___ | )o---+ | )o-o HIGH SIDE
+--|___|-+-|__/ +-|__/
|
4K7 ---
--- 100pF
|
|
===
GND

Active HIGH input 1/2 74HC132
__ __
o----+----------| \ +-| \
| ___ | )o---+ | )o-o LOW SIDE
+--|___|-+-|__/ +-|__/
|
4K7 ---
--- 100pF
|
|
===
GND
Except that these ccts will give a pulse output for each edge transition,
which is not what the OP was asking for. For a simple signal delay, the
resistor and capacitor are all that's really needed, with a buffer each
side of the passives to reshape the waveform.

Cheers,
Pete.

N

#### [email protected]

Jan 1, 1970
0
The simple rc+gate doesn't cut it as it only delays the leading edge
and thus narrows the pulse. What I'm looking to is to delay the
*whole* pulse by 500nS, whatever the width (both edges, within the
above parameters).

Cheers

P

#### Pete Wilcox

Jan 1, 1970
0
The simple rc+gate doesn't cut it as it only delays the leading edge
and thus narrows the pulse. What I'm looking to is to delay the
*whole* pulse by 500nS, whatever the width (both edges, within the
above parameters).
Ah, I see. In that case, you DO want the edge-detecting pulse generators,
using the falling edge of their outputs to drive the preset and reset
inputs of your flip-flop respectively. That will reconstruct your
original waveform with the appropriate delays on both edges. My brain
seems to have gone on holiday today without warning me...

Cheers,
Pete.

T

#### Tim Williams

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

What situation is this in? Everyone else is speaking of logic
(presumably because you are). The textbook way to go is to run your
oscillator into a T flip-flop into a pair of AND gates (well, they're
usually NOR or something, but that doesn't matter). Trick is, the
oscillator's signal is a blip (since it's really a sawtooth generator,
hence the PWM signal), so if you AND the f/f's outputs with the
oscillator, you get the deadtime implicit in the output. Another
input on the ANDs can turn off the outputs altogether, say when the
PWM comparator says "off". All of this is contained within the
SG3524 / TL494 / etc. series PWM chips, and it would not be cheating
at all to use one.

Oh, and I ask "what situation" because if you're driving MOSFETs from
a gate drive transformer, don't sweat it, just keep leakage inductance
low and it will work out. It takes more than a few nanoseconds (in
fact, whatever the rise time of the transformer is) for one gate to
turn off, the voltage to swing around, then the other to turn on. No
problem there. If you're using direct drive, then nevermind.

Tim

S

#### Spehro Pefhany

Jan 1, 1970
0
Except that these ccts will give a pulse output for each edge transition,
which is not what the OP was asking for. For a simple signal delay, the
resistor and capacitor are all that's really needed, with a buffer each
side of the passives to reshape the waveform.

Cheers,
Pete.

I presume he wants dead time to prevent overlap so the high and low
side drivers don't turn on at once and make unfortunate things happen.

We must shorten the active time of one or both signals. Shortening
just one would require a capacitor made with a hard-to-find
resublimated Thiotimoline dielectric, so it's easier to futz with
both.

Simply delaying one of the signals (otherwise keeping it the same)
will result in the leading edge not overlapping, but will *increase*
the overlap in the trailing edge, and we most likely get *ZZZZZT*
*FLASH* *KABLAM*. I love power electronics.

B

#### [email protected]

Jan 1, 1970
0
If you've got a couple of spare buffers or inverters somewhere on your cct
board, feed your signal into one then connect its output to the second one
via a resistor, with a small capacitance between the second buffer's input
and ground.  For a delay of 500nS, values of 100 ohms and 4.7nF should do
the job nicely.

This probably isn't too bad with 74HC logic, but the tolerances on the
delay won't be small when you figure out the possible range from the
worst case logic thresholds.

I wouldn't do it with 74HCT logic, and regular TTL gives you a 10:1
worst case range on the delay you get. The 74HC221 gives you much
tighter tolerances on the delay.

P

#### petrus bitbyter

Jan 1, 1970
0
I'm looking for a way to introduce a small amount of dead time into an
H-bridge. Switching frequency is up to 250kHz, so I'm looking to

I have seen a simple technique that involves delaying the drive pulse
by 1/2 the required dead time, then and/nor-ing with the base drive
signal to get the phase/anti-phase drive signals...

However, I have no idea how to implement the delay to the incoming
drive pulse by approx. that time - I have one spare 74HC75 FF in the
required, but I'm really trying to keep this simple if I can. I'm
using deicrete 74HCxx logic and would prefer not to use a specialised
drive chip with inbuilt dead-time if possible,

Thanks for any ideas...

Suppose you have two 180 degrees shifted pulses, each activating a branch of
that bridge. Now when you delay the rising edge of both of them but not the
buffers.

+---|<---+
| |
|\ | ___ | |\
--| >--+-|___|-++--| >----
|/ | |/
|
---
---
|
---------------+----------
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
(When using inverting buffers, invert the diode as well.)

petrus bitbyter

N

#### [email protected]

Jan 1, 1970
0
---
This seems to work:

Version 4
SHEET 1 2244 800
WIRE 1120 -368 16 -368 ....

The trick is to set R6C1 for the dead time you want and then to adjust
the period/frequency of the input signal to get the pulse width you need

Hi John - thanks for the input... You model works with ideal, zero
propagation, gates, but in the real world there are small timing
windows that result in spikes on the output on the falling edge of the
input signal. I can also see this in LTspice using the dview, 74HC &
74HCT libraries... I've introduced a few buffers to remove the windows
- remove pairs of them to see the effect...

Version 4
SHEET 1 880 680
WIRE -352 16 -400 16
WIRE -224 16 -272 16
WIRE -352 48 -400 48
WIRE -224 48 -272 48
WIRE -352 80 -400 80
WIRE -224 80 -272 80
WIRE -352 112 -384 112
WIRE -208 112 -272 112
WIRE -176 176 -208 176
WIRE 304 176 160 176
WIRE 448 192 416 192
WIRE 464 192 448 192
WIRE 304 208 256 208
WIRE 448 240 448 192
WIRE -208 272 -208 176
WIRE -208 272 -256 272
WIRE -176 272 -208 272
WIRE 288 272 272 272
WIRE -416 352 -416 336
WIRE -304 352 -304 336
WIRE 288 352 288 272
WIRE 304 352 288 352
WIRE -16 368 -176 368
WIRE 448 368 448 320
WIRE 448 368 416 368
WIRE 464 368 448 368
WIRE -208 384 -208 272
WIRE -176 384 -176 368
WIRE -176 384 -208 384
WIRE 112 384 96 384
WIRE 144 384 112 384
WIRE 256 384 256 208
WIRE 304 384 256 384
WIRE -176 400 -176 384
WIRE -160 400 -176 400
WIRE -48 400 -80 400
WIRE -16 400 -48 400
WIRE -48 416 -48 400
FLAG 464 192 A
FLAG 464 368 B
FLAG -48 480 0
FLAG -256 272 IN
FLAG -400 16 IN
FLAG -400 48 A
FLAG -400 80 B
FLAG -224 16 xIN
FLAG -224 48 xA
FLAG -224 80 xB
FLAG -304 432 0
FLAG -416 432 0
FLAG -304 336 VCC
FLAG -416 336 IN
FLAG 112 384 xout
FLAG -384 112 xout
FLAG -208 112 xxout
SYMBOL res -64 384 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 100R
SYMBOL cap -64 416 R0
SYMATTR InstName C1
SYMATTR Value 2.2n
SYMBOL voltage -416 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -59 -168 VRight 0
SYMATTR Value PULSE(0 5 0 2n 2n 2u 3u)
SYMATTR InstName V1
SYMBOL voltage -304 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5V
SYMBOL Digital\\dview5 -336 160 R0
SYMATTR InstName U5
SYMBOL res 432 224 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL Digital\\74HC\\74hc08 352 128 R0
SYMATTR InstName U8
SYMBOL Digital\\74HC\\74hc08 352 304 R0
SYMATTR InstName U9
SYMBOL Digital\\74HC\\74hc86 32 320 R0
SYMATTR InstName U10
SYMBOL Digital\\74HC\\74hc04 192 320 R0
SYMATTR InstName U11
SYMBOL Digital\\74HC\\74hc04 -128 112 R0
SYMATTR InstName U2
SYMBOL Digital\\74HC\\74hc04 -16 112 R0
SYMATTR InstName U1
SYMBOL Digital\\74HC\\74hc04 96 112 R0
SYMATTR InstName U3
SYMBOL Digital\\74HC\\74hc04 -128 208 R0
SYMATTR InstName U4
SYMBOL Digital\\74HC\\74hc04 -16 208 R0
SYMATTR InstName U6
SYMBOL Digital\\74HC\\74hc04 96 208 R0
SYMATTR InstName U7
SYMBOL Digital\\74HC\\74hc04 208 208 R0
SYMATTR InstName U12
TEXT -40 64 Left 0 !.tran 0 20u 0 1n
TEXT 160 0 Left 0 !.include 74hc.lib
TEXT 160 32 Left 0 !.include dview.lib

Cheers

N

#### [email protected]

Jan 1, 1970
0
<[email protected]> schreef in bericht

Suppose you have two 180 degrees shifted pulses, each activating a branchof
that bridge. Now when you delay the rising edge of both of them but not the
buffers.

+---|<---+
|        |
|\   |  ___   |  |\
--| >--+-|___|-++--| >----
|/           |   |/
|
---
---
|
---------------+----------

This is similar to an approach I'm now testing - I've been waiting for
an excuse to use some TinyLogic, and now's the time...

Cheers

Replies
1
Views
2K
Replies
11
Views
983
Replies
6
Views
9K
A
Replies
3
Views
1K
V
R
Replies
46
Views
3K
Phil Allison
P