S
Sanjayan Vinayagamoorthy
 Jan 1, 1970
 0
Hello,
I would like to simulate the following circuit:
clock1

===
^
++++
 
  Cf 
clock1 clock2 oo
  
   
=== === inm 
^ midpt^  \ 
in ++o++o\ 
  >+ out
 ++/
Cr  /
 
 
 
oo+

 GND
created by Andy´s ASCIICircuit v1.24.140803 Beta www.techchat.de
I am using winspice, and I have the following netlist:
**********
..option scale=50n
E1 out 0 0 inm 10MEG
Cr midpt 0 500f IC = 0.0V
Cf inm out 500f IC = 0.0V
M1 in clock1 midpt midpt nmos L=1 W=20
M2 midpt clock2 inm inm nmos L=1 W=20
M3 inm clock1 out out nmos L=1 W=20
Vclock1 clock1 0 DC 0 PULSE 0 1 0 0 0 2n 7n
Vclock2 clock2 0 DC 0 PULSE 0 1 3n 0 0 2n 7n
Vs in 0 dc 0.30V
..tran 100p 700n UIC
*****************
I thought that the output (out) would be equal to 0.30. However I
don't get that output. I seem to have connected everything properly,
but I have no clue what I did wrong. Any suggestions would be greatly
appreciated.
Thanks,
Regards,
Sanjay
I would like to simulate the following circuit:
clock1

===
^
++++
 
  Cf 
clock1 clock2 oo
  
   
=== === inm 
^ midpt^  \ 
in ++o++o\ 
  >+ out
 ++/
Cr  /
 
 
 
oo+

 GND
created by Andy´s ASCIICircuit v1.24.140803 Beta www.techchat.de
I am using winspice, and I have the following netlist:
**********
..option scale=50n
E1 out 0 0 inm 10MEG
Cr midpt 0 500f IC = 0.0V
Cf inm out 500f IC = 0.0V
M1 in clock1 midpt midpt nmos L=1 W=20
M2 midpt clock2 inm inm nmos L=1 W=20
M3 inm clock1 out out nmos L=1 W=20
Vclock1 clock1 0 DC 0 PULSE 0 1 0 0 0 2n 7n
Vclock2 clock2 0 DC 0 PULSE 0 1 3n 0 0 2n 7n
Vs in 0 dc 0.30V
..tran 100p 700n UIC
*****************
I thought that the output (out) would be equal to 0.30. However I
don't get that output. I seem to have connected everything properly,
but I have no clue what I did wrong. Any suggestions would be greatly
appreciated.
Thanks,
Regards,
Sanjay