# Simple Switch Capacitor Circuit

S

#### Sanjayan Vinayagamoorthy

Jan 1, 1970
0
Hello,

I would like to simulate the following circuit:

clock1

|
===
|^|
+--+|+-------+
| |
| || Cf |
clock1 clock2 o--||--------o
| || |
| | | |
=== === |inm |
|^| midpt|^| | |\| |
in ----+|+--o---+|+--o---|-\ |
| | >-----+ out
| +---|+/
Cr--- | |/|
--- |
| |
| |
---------o---o----+
|
--- GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

I am using winspice, and I have the following netlist:

**********
..option scale=50n

E1 out 0 0 inm 10MEG

Cr midpt 0 500f IC = 0.0V
Cf inm out 500f IC = 0.0V

M1 in clock1 midpt midpt nmos L=1 W=20
M2 midpt clock2 inm inm nmos L=1 W=20
M3 inm clock1 out out nmos L=1 W=20

Vclock1 clock1 0 DC 0 PULSE 0 1 0 0 0 2n 7n
Vclock2 clock2 0 DC 0 PULSE 0 1 3n 0 0 2n 7n

Vs in 0 dc 0.30V

..tran 100p 700n UIC
*****************

I thought that the output (out) would be equal to -0.30. However I
don't get that output. I seem to have connected everything properly,
but I have no clue what I did wrong. Any suggestions would be greatly
appreciated.

Thanks,

Regards,
Sanjay

J

#### Joe Legris

Jan 1, 1970
0
Sanjayan said:
Hello,

I would like to simulate the following circuit:

clock1

|
===
|^|
+--+|+-------+
| |
| || Cf |
clock1 clock2 o--||--------o
| || |
| | | |
=== === |inm |
|^| midpt|^| | |\| |
in ----+|+--o---+|+--o---|-\ |
| | >-----+ out
| +---|+/
Cr--- | |/|
--- |
| |
| |
---------o---o----+
|
--- GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

I am using winspice, and I have the following netlist:

**********
.option scale=50n

E1 out 0 0 inm 10MEG

Cr midpt 0 500f IC = 0.0V
Cf inm out 500f IC = 0.0V

M1 in clock1 midpt midpt nmos L=1 W=20
M2 midpt clock2 inm inm nmos L=1 W=20
M3 inm clock1 out out nmos L=1 W=20

Vclock1 clock1 0 DC 0 PULSE 0 1 0 0 0 2n 7n
Vclock2 clock2 0 DC 0 PULSE 0 1 3n 0 0 2n 7n

Vs in 0 dc 0.30V

.tran 100p 700n UIC
*****************

I thought that the output (out) would be equal to -0.30. However I
don't get that output. I seem to have connected everything properly,
but I have no clue what I did wrong. Any suggestions would be greatly
appreciated.

Thanks,

Regards,
Sanjay

My nephew just went through this exercise with an almost identical
circuit. His problems:

1) His mosfets were too big - choose smaller dimensions. The effective
interelectrode capacitances should be much smaller than your switched
capacitors.

2) Connect the substrates of the mosfets to ground. If you use any
p-channel mosfets connect the substrates to Vcc.

3) You must run the analysis for a sufficient # of clock cycles (10 or
so) for the capacitors to charge and the output to stabilize.

I seem to recall that we had trouble getting the clocks to run on
transient analysis - make sure they're active. Eventually it worked fine.

S

#### Sanjayan Vinayagamoorthy

Jan 1, 1970
0
Sanjayan said:
My nephew just went through this exercise with an almost identical
circuit. His problems:
1) His mosfets were too big - choose smaller dimensions. The effective
interelectrode capacitances should be much smaller than your switched
capacitors.

I varied the size of the transistors but this had no effect on the
output.
2) Connect the substrates of the mosfets to ground. If you use any
p-channel mosfets connect the substrates to Vcc.

Right now, I have connected bulk to source, to negate Vt shifts. I
don't have any pmos transistors.
3) You must run the analysis for a sufficient # of clock cycles (10 or
so) for the capacitors to charge and the output to stabilize.

I set the clock period to 4ns and and I am looking at the output
1000ns later.
I seem to recall that we had trouble getting the clocks to run on
transient analysis - make sure they're active. Eventually it worked fine.

I know I must be making some silly mistake. There's no reason why this
shouldn't work. But thanks for the suggestions.

Regards,
Sanjay

J

#### Joe Legris

Jan 1, 1970
0
Sanjayan said:
I varied the size of the transistors but this had no effect on the
output.

Right now, I have connected bulk to source, to negate Vt shifts. I
don't have any pmos transistors.

That's part of your problem. The clock signals are referred to ground
but the Vt of the mosfets are referred to the signal levels. For
example, when the input signal is 0.3V the first mosfet's effective Vt
will be raised by 0.3V. What if the input signal is +2.5V?

Does your op-amp have positive and negative power connections? I don't
see any.

For troubleshooting, start by observing the voltage at every node to get
some clues. Write them all down and show us what they are, including the
power connections.

You may also try breaking the circuit into simpler blocks. For example,
split off the the first mosfet and Cr. Does it charge to 0.3V?

Does the op-amp work? Try replacing the switched mosfets with resistors.
What happens?

--
Joe Legris
============================================================================
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P

#### pkh

Jan 1, 1970
0
When using MOSFETs as switches (also called t-gates or transmission
gates), you don't know which side of the device is the source! You must
tie the bulk to the appropriate supply! The nMOS device is symmetric,
and the source is defined as the n+ diffusion at the lowest potential
(the drain is at the higher potential). If the voltage is higher on left
side, then the right side is the source, and vice versa. If you tie the
bulk to the higher potential, you now have a forward biased bulk diode!

To see this more clearly, draw in the body diodes for the nMOS device.
The p-substrate bulk and the n+ diffusions (source & drain) form the pn
junctions. So you have a diode from bulk to source (arrow pointing from
bulk to source), and another from bulk to drain (arrow pointing from
bulk to drain). You'll see very quickly what happens if you tie the bulk
to the higher potential!!

Regards,

Paul

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