Maker Pro
Maker Pro

Single ended LVDS into FPGA

N

Nico Coesel

Jan 1, 1970
0
Some food fo thought:

I'm working on a new design in which I need to bring 64 LVDS (250Mbps
each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between
the source and the FPGA is less than 2" / 5cm. Ofcourse there is a
solid ground plane underneath the signals (the board will have at
least 4 layers).

I'm wondering if I can save a lot of pins if I feed the LVDS signals
single ended into the FPGA (terminate the pair close to the FPGA and
leave one end dangling). I could bias the Vref pins on the FPGA to the
centre point of the LVDS signal. If I set the input pin type to GTL it
should work on paper. The LVDS signal has enough swing to exceed the
minimum signal amplitude.

Anyone ever tried this?
 
N

Nico Coesel

Jan 1, 1970
0
BobW said:
The thing that would concern me is how to guarantee that VREF is held at the
centerpoint (common mode) of the signal swing. If you were only dealing with

The datasheet of the source chip specifies that. I more or less assume
the source chip has the same centerpoint on all outputs.
one pair then you get tricky and extract the common-mode point from that
pair - assuming that the signal was always transitioning. Knowing that

IMHO you don't need a signal that is always toggling. If you connect a
resistor to each leg of the pair and a capacitor to ground (resistor
divider between the two legs) then the voltage across the capacitor
should be the centre voltage no matter what the LVDS signal looks
like.
 
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