Sizing Mosfet Gate Resistors

[Eeyore]

QED: Eeyore has been proven incompetent ;-)

Pppfffttttt !

I was on the right track !

Graham

 

[Terry Given]

Terry Given wrote:




Eh ? Q . t^-1 = I

LOL. I cant read....

OK. Neat trick. Hadn't figured that one.





Just the rate. Of course it it was very slow the gate would never charge to V.

correct, and the analysis then gets slightly harder.

Interesting.

Graham

HTH


next interesting question: what about using a bipolar drive (+/-15V) and
resistor? I'll leave the analysis as an exercise for the interested reader


Cheers
Terry

 

[Eeyore]

LOL. I cant read....


correct, and the analysis then gets slightly harder.


HTH

next interesting question: what about using a bipolar drive (+/-15V) and
resistor? I'll leave the analysis as an exercise for the interested reader

Instinctively I'd treat it as equivalent to 30V unipolar.

Graham

 

[John Woodgate]

During a vacation job back in the college days I build many of these.
About the size of a Westinghouse fridge when complete. I guess they are
still doing their job in locomotives (in Brazil).

Surface-mounted devices. With BIG bolts. (;-)

 

[Fred Bloggs]

QED: Eeyore has been proven incompetent ;-)

...Jim Thompson

They're both incompetent because the MOSFET Cin is nonlinear, time
varying, and a complicated function of gate driver performance. It is
not necessary to compute the gate resistor power dissipation to any
great accuracy, it is only necessary to bound it. The gate resistor
power handling will usually be derated by a factor of two minimum. A
more usable estimate simply works on worst-case rise and fall times of
Vgs, derived from manufacturer total gate charge requirements and driver
characteristics, like so:
View in a fixed-width font such as Courier.

 

[Fred Bloggs]

The gate resistors are in series with the gates but they are all driven
from a single source.

My test stratgey is:

1 - ground the common signal source
2 - apply an appropriate pulse at the test point beween one Fet and its
gate resistor
3 - acquire the Vds data (gppib data from oscioscope) before during and
after the "appropriate gate pulse"
4 - crunch Vds to see that the correct "dip" is there for a Fet sinking
some current.

That so-called test is not representative of any actual circuit stress
on the gate resistors. A simple calculation, as in my first post, shows
that the average power dissipation in the gate resistor is inversely
proportional to Rg and directly proportional to the transition times. If
the transition times are proportional to RgxCin, as one might expect,
then the average power dissipated in Rg is independent of Rg and in
direct proportion to a F*Cpd*Vg^2 product, where Cpd is a parameter
similar to that specified for the CMOS logic families as a means to
estimate power dissipation with frequency. The reason why a Cpd cannot
be universally applied to power MOSFETs is that Cpd will be load
dependent. As others have stated, it may not be power so much as peak
current handling capability of the Rg that is in question.

 

[John Larkin]

dont bother, its wrong. The basic maths is:

E = 0.5*Q*V = 0.5*C*V^2

P = E*f

do a dimensional analysis (IOW look at the units) of your equation, they
dont match.

When you put 0.5*C*V^2 J into a cap thru a resistor, the resistor also
dissipates 0.5*C*V^2 J. When you then discharge the cap into the same
resistor, again it dissipates 0.5CV^2 J, leading to a total resistor
energy loss of CV^2 J to charge C to V Volts then discharge C. Repeat at
some frequency F, and voila: P = CV^2F

The resistor doesnt appear in the equation because it is not controlling
the voltage to which the cap gets charged.

The above assumes the cap is both fully charged and discharged.

It also assumes that the drive is much faster than the tau of the
resistor*gate capacitance.

John

 

[EdV]

Sounds sensible.



Which voltage ?


This all sounds a bit arse about face to me.

Graham

You and me both.

Ed V.

 

[Fred Bloggs]

It also assumes that the drive is much faster than the tau of the
resistor*gate capacitance.

John

Since an effective transition time is an RMS of the two, the driver need
only transition ~10x faster to make its contribution negligible. This is
a reasonable constraint for specialized driver ICs and most worthwhile
improvised substitutions.

 

[Jim Thompson]

They're both incompetent because the MOSFET Cin is nonlinear, time
varying, and a complicated function of gate driver performance. It is
not necessary to compute the gate resistor power dissipation to any
great accuracy, it is only necessary to bound it. The gate resistor
power handling will usually be derated by a factor of two minimum. A
more usable estimate simply works on worst-case rise and fall times of
Vgs, derived from manufacturer total gate charge requirements and driver
characteristics, like so:
View in a fixed-width font such as Courier.


.
.
. 2
. (Vin-Vgs) Vin
. P (t)= --------- & Vgs= --- x t
. R R Tr
.
. 2 Tr
. V / 2
. in | t 2 Vin Tr
. -> E = --- * | (1 - --) dt = --- * --
. R R | Tr R 3
. /
. 0
. 2
. Vin Tf
. Similarly on fall E = --- * --
. R R 3
.
.
.
. 2
. Vin
. P = --- x F x T , T = Tr + Tf , F=frequency
. R,AVG 3R T T
.
.
.

I don't know that I'd describe Cin as "non-linear", but you have a
point. There is a region where the gate "eats" charge, but doesn't
change voltage. I suspect you can analyze the power dissipated in a
far simpler fashion than you suggest.

...Jim Thompson

 

[John Woodgate]

In message <[email protected]>, dated Thu, 31

I don't know that I'd describe Cin as "non-linear", but you have a
point. There is a region where the gate "eats" charge, but doesn't
change voltage. I suspect you can analyze the power dissipated in a
far simpler fashion than you suggest.

If the device model is good, LT Spice will tell you what the dissipation
in the resistor is.

 

[Jim Thompson]

In message <[email protected]>, dated Thu, 31


If the device model is good, LT Spice will tell you what the dissipation
in the resistor is.

Yep, ANY SPice will calculate it correctly IF the model is good...
PSpice Level=7, or HSpice Level=28 or Level=49

...Jim Thompson

 

[EdV]

That so-called test is not representative of any actual circuit stress
on the gate resistors. A simple calculation, as in my first post, shows
that the average power dissipation in the gate resistor is inversely
proportional to Rg and directly proportional to the transition times. If
the transition times are proportional to RgxCin, as one might expect,
then the average power dissipated in Rg is independent of Rg and in
direct proportion to a F*Cpd*Vg^2 product, where Cpd is a parameter
similar to that specified for the CMOS logic families as a means to
estimate power dissipation with frequency. The reason why a Cpd cannot
be universally applied to power MOSFETs is that Cpd will be load
dependent. As others have stated, it may not be power so much as peak
current handling capability of the Rg that is in question.

The test is to make sure the fets are soldered to the PWB. The
problem is the 10 ohm gate resistors for 10 fets are daisy chained to
the same signal source.

The other problem is of course I ask more than one question at a time.


Thanks to all. I get quite an education posting here. I will remember
to spell check next time.

Ed V.

 

[Winfield Hill]

Joerg wrote...

Hello John,

I'm not so sanguine. Most of the energy is dissipated in very
small volumes, before spreading out to the rest of the package.
It's easy to blow them out without significant package heating.
I agree with Joerg, be careful. I've had to replace more than
a few surface-mount resistors in multiple types and designs of
commercial products, where I think the failures were due to the
poor peak-power capability of the resistor. We're talking from
a reference filter in a commercial power supply, to an offline
regulator in my tech's Kenmore washing machine's DSP VFD motor
controller (after working properly for five years = past the
warranty).

A typical SMD resistor seems much more fragile than the older
already-fragile film resistors.

It looks like some engineers aren't taking the conservative
peak-power specs typically found in a data sheet seriously,
perhaps because they got used to better in the old days.

Don't discount pulse load limits. Metal film types exhibit certain
pathologies related to that. That is a serious concern with most of
my ultrasound pulser designs. I used to prefer Beyschlag because of
their excellent specsmanship. They were bought by Vishay but much of
the info is now online: http://www.vishay.com/docs/49280/tn0006.pdf

Those "professional thin film MELF resistors" look impressive.

They are also very helpful on the phone but if it's still like it
used to be, ideally you'd have to be able to speak German. Preferably
with a northern accent ;-)

Do you have any specific data on peak-power vs time profiles in
cases where you got into trouble with ordinary SMD parts?

 

[legg]

Capability" circa Thurs, Feb 26 2004 :

"This is a common reliability problem with power electronics -
"designers"
often neglect peak pulse power in MOSFET gate resistors - I saw one
design
with 4.7Ohm Rg, +12V Vg i.e. 31W peak, using 0805 resistors that failed

after a short time, causing catastrophic failure; so much damage was
done
each time that the root cause was totally obscured, and the "designer"
could
not stop it happening. oops. "

I am the lowly test engineer with the 10 fets in parallel test question
from several months ago. I the process of getting my head around how
hard I can pulse my 10 ohm gate resistors when one side itied to
ground. I read Terry's above note.

Anyone care to elaborate or point me to a good app note regarding
sizing Mosfet gate resistors?

The board I am testing (yes "they" decided the mosfets need to be
individually turned on. . .I knew "they" would) looks suspicously like
"oops".

An open gate resistor is not neccessarily the source of upset - it is
however quite commonly the end result.

Peak power can be a factor in device reliability;

http://www.irctt.com/pdf_files/PWCR.pdf
http://www.welwyn-tt.com/pdf/datasheet/PWC.PDF

In fixed frequency operation power loss is determined by
C * V^2 * f , as the power dissipated in the resistor occurs twice in
each cycle. Normal energy loss in a single unidirectional pulse is
( C * V^2 ) / 2 , in joules.

Note that this is independant of R, in so much that the R of the
series limiter in question still dominates. If there are other series
lossy elements, the total power loss is shared proportional to R.

At 100 KHz, an 0805 part is safe driving a 10V signal into a 10nF
gate, ignoring the effect of Cgd, at an 80% power stress rating,
provided it has sufficient copper connected to dissipate .125W.

RL

 

[legg]

They're both incompetent because the MOSFET Cin is nonlinear, time
varying, and a complicated function of gate driver performance. It is
not necessary to compute the gate resistor power dissipation to any
great accuracy, it is only necessary to bound it. The gate resistor
power handling will usually be derated by a factor of two minimum. A
more usable estimate simply works on worst-case rise and fall times of
Vgs, derived from manufacturer total gate charge requirements and driver
characteristics, like so:
View in a fixed-width font such as Courier.


.
.
. 2
. (Vin-Vgs) Vin
. P (t)= --------- & Vgs= --- x t
. R R Tr
.
. 2 Tr
. V / 2
. in | t 2 Vin Tr
. -> E = --- * | (1 - --) dt = --- * --
. R R | Tr R 3
. /
. 0
. 2
. Vin Tf
. Similarly on fall E = --- * --
. R R 3
.
.
.
. 2
. Vin
. P = --- x F x T , T = Tr + Tf , F=frequency
. R,AVG 3R T T

Using total gate charge (including reverse transfer) is as much as
it's probably worth, even though this is a nominal value and has to be
factored for drain voltage.

If thee are other sources of drain voltage movement, they add further
charges to the burden.

RL

 

[legg]

On Thu, 31 Aug 2006 04:05:17 +0100, Eeyore

Instinctively I'd treat it as equivalent to 30V unipolar.

The total gate charge spec only assumes 0V origins, but despite other
words to the contrary, once the drain has stopped changing voltage,
the gate capacitance is quite linear and energy state changes from
zero can be simply added.

RL

 

[legg]

Since an effective transition time is an RMS of the two, the driver need
only transition ~10x faster to make its contribution negligible. This is
a reasonable constraint for specialized driver ICs and most worthwhile
improvised substitutions.

Depends on whether the driver is resistive or current delivering. The
first assumes it's share of the total calculated losses, the second
has losses that are more related to average current.

RL

 

[Joerg]

Hello Win,

A typical SMD resistor seems much more fragile than the older
already-fragile film resistors.

The least fragile were grampa's old carbon resistors. They could take a
punch.

It looks like some engineers aren't taking the conservative
peak-power specs typically found in a data sheet seriously,
perhaps because they got used to better in the old days.

I have come across resistors where there was no peak power spec :-(

Those "professional thin film MELF resistors" look impressive.

I have always liked MELFs. Wonderful parts but often no fun for the
assembly plant.

Do you have any specific data on peak-power vs time profiles in
cases where you got into trouble with ordinary SMD parts?

Unfortunately not anymore. I got that data from Beyschlag (now Vishay)
and similar data from AVX for ceramic caps because we were stressing
some of those as well. Both companies were excellent in furnishing data
beyond what's in the spec sheets.

The problem has subsided a bit because we don't have to "beat FETs over
the head" anymore to get performance. But it'll come back with the
migration to 0402 and smaller because everything has to be the size of
an iPod now.

 

[Joerg]

Hello Jim,

Yep, ANY SPice will calculate it correctly IF the model is good...
PSpice Level=7, or HSpice Level=28 or Level=49

Can Spice also show you the location and size of the crater that
develops when it "needs to vent"? Happened recently. A volcano appeared
on the SOT23 package, a wee puff and then a stench wafted through the
room. Miraculously the device was still working to some extent.