Maker Pro
Maker Pro

Smart autorouting tool capable of optimal net connection.

M

Maaf

Jan 1, 1970
0
When designing a system (computer) with a 32-bit data bus that is
connected to 4 SRAM chips in parallel, each 8-bit wide, the usual (but
not optimal) approach would be to connect pin D0 from SRAM chip 0 to
processor's D0, D1 from SRAM chip 0 to processor's D1 and so on.
However, if we allow the data lines to be interchanged when connecting
to the memory chips possibly we could end with a more optimized board
layout. Hence I would like to have a schematic/PCB tool were we can
specify that each line from the data bus should be connected to a
single data pin in the memory bank, but without specifying the
connection order. The exact connection between the memory bank data
pins and system data lines would be defined only after routing the
board.
A possible way to specify this in a schematic editor could be as
shown in the following pictures (available in .bmp, .png and .jpg file
formats):
http://www.geocities.com/maaf1980/maaf/optimized_memory_connection.png
http://www.geocities.com/maaf1980/maaf/optimized_memory_connection.jpg
http://www.geocities.com/maaf1980/maaf/optimized_memory_connection.bmp
In this picture, U1 is the processor, U2 to U5 are SRAM chips, and
BW1 specifies how the processor data bus D[31:0] connects to the SRAM
chips (Here represented by the MD[31:0] bus, where MD31 is the U2/D7
pin, MD30 is the U2/D6 pin, ..., MD0 is the U5/D0 pin.). BW1 doesn't
exist as a component in the board layout, it is defined by the
autorouting tool in such a manner to make the board layout as optimal
as possible. For instance, SW1 could be for a certain design:
D0 = MD7
D1 = MD8
D2 = MD9
D3 = MD1
D4 = MD2
...
After the routing completes, the autorouting tool should generate a
report documenting how the connection between D[31:0] and MD[31:0] has
been done in BW1.

Do you know any SCH/PCB layout tool capable of doing this? Also, is
there any pitfalls, drawbacks or caveats when interchanging data lines
or address lines in SRAM memories in order to archieve an optimal board
design?

Best Regards,
Márcio.
 
When designing a system (computer) with a 32-bit data bus that is
connected to 4 SRAM chips in parallel, each 8-bit wide, the usual (but
not optimal) approach would be to connect pin D0 from SRAM chip 0 to
processor's D0, D1 from SRAM chip 0 to processor's D1 and so on.
However, if we allow the data lines to be interchanged when connecting
to the memory chips possibly we could end with a more optimized board
layout. Hence I would like to have a schematic/PCB tool were we can
specify that each line from the data bus should be connected to a
single data pin in the memory bank, but without specifying the
connection order. The exact connection between the memory bank data
pins and system data lines would be defined only after routing the
board.
A possible way to specify this in a schematic editor could be as
shown in the following pictures (available in .bmp, .png and .jpg file
formats):
http://www.geocities.com/maaf1980/m...maaf1980/maaf/optimized_memory_connection.bmp
In this picture, U1 is the processor, U2 to U5 are SRAM chips, and
BW1 specifies how the processor data bus D[31:0] connects to the SRAM
chips (Here represented by the MD[31:0] bus, where MD31 is the U2/D7
pin, MD30 is the U2/D6 pin, ..., MD0 is the U5/D0 pin.). BW1 doesn't
exist as a component in the board layout, it is defined by the
autorouting tool in such a manner to make the board layout as optimal
as possible. For instance, SW1 could be for a certain design:
D0 = MD7
D1 = MD8
D2 = MD9
D3 = MD1
D4 = MD2
...
After the routing completes, the autorouting tool should generate a
report documenting how the connection between D[31:0] and MD[31:0] has
been done in BW1.

Do you know any SCH/PCB layout tool capable of doing this? Also, is
there any pitfalls, drawbacks or caveats when interchanging data lines
or address lines in SRAM memories in order to archieve an optimal board
design?

Best Regards,
Márcio.


Hi Márcio

Most pro schematic/ layout tools have a way to make pins swappable,
this way you can swap pins on a resistor network or swap gates on a
quad or-gate IC.

The only pitfall is that you must ensure that pins only swap within
the memory chip and not across chips. For example, if you have three
quad and-gate IC's on a board, if the gates are all the same class
then the tool can move the gate to another IC. In your case you don't
want that to happen.

I have used PCAD, PADS and ORCAD and they all have the capability to
do this.
 
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