Hello,
Sorry, perhaps I worded this question incorrectly. I don't expect
spice to able to calculate parasitic capacitances that put there. I.e,
if I model an inductor, and I specifically place a parasitic
capacitance within the model of the inductor then spice knows it
exists and should take into account. Usually I will place all the
parasitics on the schematic and some of them should be implied as
well. (When you place a transistor, you should tell spice only what
the unit gate capacitance is and it should be able to figure out the
total gate capacitance...correct?) However when the schematic gets
large, it is quite easy for me to forget all the parasitics that are
connected to that specific node, but spice should know what those are.
I was wondering, if I could spice to spit it for me, so that I don't
accidentally forget something.
Best Regards,
WHY do you think Spice will know about parasitics if you don't tell
it?? I'll repeat, Spice only models what you explicitly put into its
netlist. If you think there is parasitic capacitance from one node to
another (possibly to ground, for example) that's big enough it will
significantly affect the performance of your circuit, then figure out
how much capacitance there is in your physical implementation, and put
it in the model. Spice does not work from a physical model, it works
from a mathematical abstraction. It's up to you to make sure the
physical world is accurately described by the information you feed
Spice about your circuit. If you're dealing with semiconductor design
there may be special issues someone like Jim Thompson (who posts
regularly here) could help with.
There ARE design programs that take into account the physical layout,
treating printed circuit traces and pads as transmission lines with
distributed capacitance and inductance. The Spice engine is not one
of those. In some versions of Spice, including LTSpice, you can
create a library of models of specific parts like inductors that
include at least limited parasitic information like series resistance,
shunt resistance and shunt capacitance. Capacitors in LTSpice can
include parasitics. Spice models for semiconductors have lots of
parameters to describe the semiconductor behaviour (including voltage-
dependent capacitance, resistances you might wish were zero but are
not, ...), but do not include package inductance, capacitance, and
resistance. Some manufacturers' models of packaged semiconductors do
include those effects.
But if you accidentally forget to put a critical coupling capacitor in
your circuit, would you expect Spice to tell you, "Hey, you forgot to
put in a capacitor here. You probably want 0.22uF, so I put it in for
you." No? Then don't expect it to think of what parasitics might be
in your physical implementation that you left out of your model.
Cheers,
Tom