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Synchronizing T-flops?

J

Jim Thompson

Jan 1, 1970
0
The problem...

Running from a 2.2 GHz clock and squeezing power, I'm using T-flops
(toggle-flops).

I DIV2 on positive edge to get 1.1GHz
I also DIV2 on negative edge to get 1.1GHz but shifted +/- 90°

Continuing with the dividing I get down also to...

137.5MHz
and 137.5MHz, angle +/- 90

I want to mix the 1.1GHz and 137.5MHz signals to get either 1.2375GHz
or 962.5MHz in a image-reject mixer

The snag...

The sum/difference depends on phasing of each component, but, since
each of the final components started out from toggle flops the final
sign of the 90° is unknown.

Anyone have clever ideas to determine whether each component is + or -
90° ??

If I can determine phase I can flip to the correct phase thru a PECL
inverter.

If I can solve this then the system can simply call for high or low
sideband and be assured its the right one.

Right now it's random :-(

This is on an ASIC, so I must DESIGN the circuit, NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip.

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
The problem...

Running from a 2.2 GHz clock and squeezing power, I'm using T-flops
(toggle-flops).

I DIV2 on positive edge to get 1.1GHz
I also DIV2 on negative edge to get 1.1GHz but shifted +/- 90°

Continuing with the dividing I get down also to...

137.5MHz
and 137.5MHz, angle +/- 90

I want to mix the 1.1GHz and 137.5MHz signals to get either 1.2375GHz
or 962.5MHz in a image-reject mixer

The snag...

The sum/difference depends on phasing of each component, but, since
each of the final components started out from toggle flops the final
sign of the 90° is unknown.

Anyone have clever ideas to determine whether each component is + or -
90° ??

If I can determine phase I can flip to the correct phase thru a PECL
inverter.

If I can solve this then the system can simply call for high or low
sideband and be assured its the right one.

Right now it's random :-(

This is on an ASIC, so I must DESIGN the circuit, NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip.

...Jim Thompson

You need some d-flops.

John
 
J

Jim Thompson

Jan 1, 1970
0
You need some d-flops.

John

At 2.2GHz the process was failing some corners when I tried starting
with D's

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
At 2.2GHz the process was failing some corners when I tried starting
with D's

...Jim Thompson


You could do the dual t-flops to get to 1.1G, like you propose, then
use a d-flop running at 1.1 to determine if the t's are in the desired
phase sequence or not. Use that info to flip the phase of the 137.5 to
select the proper mixer output freq.

Or something.

How much image rejection do you need? Keeping close to 90 degrees at
1.1G won't be easy. 1 degree is just a few ps.


John
 
Z

Zak

Jan 1, 1970
0
Jim said:
If I can solve this then the system can simply call for high or low
sideband and be assured its the right one.

Right now it's random :-(

Test it using some test tone, see what the phase is, and act
accordingly? This might need firmware support.

Or: use a delay (RC?) and a transmission gate to figure out the phase.


Thomas
 
R

Rene Tschaggelar

Jan 1, 1970
0
Jim said:
The problem...

Running from a 2.2 GHz clock and squeezing power, I'm using T-flops
(toggle-flops).

I DIV2 on positive edge to get 1.1GHz
I also DIV2 on negative edge to get 1.1GHz but shifted +/- 90°

Continuing with the dividing I get down also to...

137.5MHz
and 137.5MHz, angle +/- 90

I want to mix the 1.1GHz and 137.5MHz signals to get either 1.2375GHz
or 962.5MHz in a image-reject mixer

The snag...

The sum/difference depends on phasing of each component, but, since
each of the final components started out from toggle flops the final
sign of the 90° is unknown.

Anyone have clever ideas to determine whether each component is + or -
90° ??

AND, AND Not
If I can determine phase I can flip to the correct phase thru a PECL
inverter.

.. flip the phase with an inverter ?
That stuff is not that fast. If the inverter is just
introducing 100ps delay, that amounts to a phase error
of some degrees.

Rene
 
F

Fred Bartoli

Jan 1, 1970
0
Jim Thompson said:
The problem...

Running from a 2.2 GHz clock and squeezing power, I'm using T-flops
(toggle-flops).

I DIV2 on positive edge to get 1.1GHz
I also DIV2 on negative edge to get 1.1GHz but shifted +/- 90°

Continuing with the dividing I get down also to...

137.5MHz
and 137.5MHz, angle +/- 90

I want to mix the 1.1GHz and 137.5MHz signals to get either 1.2375GHz
or 962.5MHz in a image-reject mixer

The snag...

The sum/difference depends on phasing of each component, but, since
each of the final components started out from toggle flops the final
sign of the 90° is unknown.

Anyone have clever ideas to determine whether each component is + or -
90° ??

If I can determine phase I can flip to the correct phase thru a PECL
inverter.

If I can solve this then the system can simply call for high or low
sideband and be assured its the right one.

Right now it's random :-(

This is on an ASIC, so I must DESIGN the circuit, NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip.


Why don't you divide down to 550MHz with your T flops (only one chain), then
divide by 4 with a ring counter.

Only 2 T flops, and 2 D flops that run at low frequency.

You know which output is which phase and this is probably even lower power
than 2 dividers chains.
 
C

Chris Cheney

Jan 1, 1970
0
In addition to the two Ts, you need one D f/f (at 1.1 GHz) to determine the
phase to control the PECL inverter that you (Jim) originally proposed. 137.5
MHz similarly.

By way of more explanation, take the reference (0 deg) 1.1 GHz signal to the
D-clock input, and the + or - 90 signal to the D-input. If the 90 leads then
the D output will be 1 and if it lags it will be 0.

HTH
 
J

Jim Thompson

Jan 1, 1970
0
In addition to the two Ts, you need one D f/f (at 1.1 GHz) to determine the
phase to control the PECL inverter that you (Jim) originally proposed. 137.5
MHz similarly.

By way of more explanation, take the reference (0 deg) 1.1 GHz signal to the
D-clock input, and the + or - 90 signal to the D-input. If the 90 leads then
the D output will be 1 and if it lags it will be 0.

HTH

Aha! I think that will work. I'm thinking that, since I'm producing
SSB, I only need to _know_ the 1.1GHz and 137.5MHz phase, and flip
ONLY the 137.5MHz accordingly, to get a known sum or difference (high
or low sideband).

In case anyone is pondering... I, the Great God of Analog, made a
blooper...

Designed a chip, everything works perfectly, except... on power-up,
it's random as to which side band it's on :-(

However, since there's already a switch in the logic to pick low or
high sideband, I'll just add Chris' D-flop and then some logic to the
switch path.

Thanks!

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
However, since there's already a switch in the logic to pick low or
high sideband, I'll just add Chris' D-flop and then some logic to the
switch path.

I thought it was my flipflop.

John
 
J

Jim Thompson

Jan 1, 1970
0
I thought it was my flipflop.

John

You were too vague for El Denso to understand... us analog guys need
pictures ;-)

...Jim Thompson
 
J

John Fields

Jan 1, 1970
0
Aha! I think that will work. I'm thinking that, since I'm producing
SSB, I only need to _know_ the 1.1GHz and 137.5MHz phase, and flip
ONLY the 137.5MHz accordingly, to get a known sum or difference (high
or low sideband).

In case anyone is pondering... I, the Great God of Analog, made a
blooper...

Designed a chip, everything works perfectly, except... on power-up,
it's random as to which side band it's on :-(

However, since there's already a switch in the logic to pick low or
high sideband, I'll just add Chris' D-flop and then some logic to the
switch path.

---
So,

"This is on an ASIC, so I must DESIGN the circuit,NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip."

should really have read more like:

"This is on an ASIC, and I don't know how to DESIGN the circuit, so
any FREE help would be appreciated."
 
A

Andy

Jan 1, 1970
0
John said:
You could do the dual t-flops to get to 1.1G, like you propose, then
use a d-flop running at 1.1 to determine if the t's are in the desired
phase sequence or not. Use that info to flip the phase of the 137.5 to
select the proper mixer output freq.

Or something.

How much image rejection do you need? Keeping close to 90 degrees at
1.1G won't be easy. 1 degree is just a few ps.


John

Another variation: use just 1 T-flop flopping on the negative edge of
the input clock, and feed its output to the D-flop latching on the
positive edge of the input clock. That way the D-flop's output will
always lag 90 degrees the T-flop's one. This would save a flop, but
might have the inconvenience of non-equal propagation delays of the T-
and D-flops.

-- Andy
 
J

James Beck

Jan 1, 1970
0
---
So,

"This is on an ASIC, so I must DESIGN the circuit,NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip."

should really have read more like:

"This is on an ASIC, and I don't know how to DESIGN the circuit, so
any FREE help would be appreciated."

John Fields
Professional Circuit Designer
Jeez, take a chill pill.
More like, he needed to bounce a few ideas around, and USENET is a free
and easy way to do that. I guess you have NEVER used any info you have
found here, you just hang out to make fun of the vast unwashed......
Oh, I guess I missed the "Professional Circuit Designer ", never mind.

Jim
 
J

John Larkin

Jan 1, 1970
0
You were too vague for El Denso to understand... us analog guys need
pictures ;-)

...Jim Thompson


Well, I just sort of figured that there aren't a whole lot of
different ways to connect two signals to the inputs of a d-type
flipflop.

John
 
L

Lasse Langwadt Christensen

Jan 1, 1970
0
Andy said:
John Larkin wrote:
snip


Another variation: use just 1 T-flop flopping on the negative edge of
the input clock, and feed its output to the D-flop latching on the
positive edge of the input clock. That way the D-flop's output will
always lag 90 degrees the T-flop's one. This would save a flop, but
might have the inconvenience of non-equal propagation delays of the T-
and D-flops.

yep, keeping the two paths the same is probably a good idea,
that's the nice part about doing it by sampling I with Q to get the
lead/lag, instead of changing the I/Q generation scheme which it
sounds like has been verified in silicon

-Lasse
 
J

Jim Thompson

Jan 1, 1970
0
Jeez, take a chill pill.
More like, he needed to bounce a few ideas around, and USENET is a free
and easy way to do that. I guess you have NEVER used any info you have
found here, you just hang out to make fun of the vast unwashed......
Oh, I guess I missed the "Professional Circuit Designer ", never mind.

Jim

Mr. Beck, Don't let John Fields upset you. He is required to keep
spouting absurd inanities in order to maintain his status as resident
village idiot ;-)

...Jim Thompson
 
J

John Fields

Jan 1, 1970
0
Jeez, take a chill pill.
More like, he needed to bounce a few ideas around, and USENET is a free
and easy way to do that. I guess you have NEVER used any info you have
found here, you just hang out to make fun of the vast unwashed......
Oh, I guess I missed the "Professional Circuit Designer ", never mind.

---
Don't like the attitude, huh? Too bad.
Don't like the dotsig, huh? Also too bad.

Think you've got something to say? You don't, but dumbfucks like you
don't seem to be able to come to that realization without some kind of
outside help, so here it is:

You're an ignorant son of a bitch and you have nothing important to
contribute to this group (sed). That is, out of nine posts only three
were on topic (one only marginally) and the rest were all off-topic,
inane garbage. Why don't you take a hike over to alt.cocksuckers,
where I'm sure you'll find a more appreciative audience.
 
J

John Larkin

Jan 1, 1970
0
Dang, John, you and Chris are _quick!_

I was gonna answer this one! :)


Well, free engineering consulting is a very competitive business.

John
 
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