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Synchronizing T-flops?

J

John Larkin

Jan 1, 1970
0
Jeez, take a chill pill.
More like, he needed to bounce a few ideas around, and USENET is a free
and easy way to do that. I guess you have NEVER used any info you have
found here,


JF designs only with 555 timers, so he never needs to ask questions.


John
 
J

John Fields

Jan 1, 1970
0
Mr. Beck, Don't let John Fields upset you. He is required to keep
spouting absurd inanities in order to maintain his status as resident
village idiot ;-)
 
J

John Larkin

Jan 1, 1970
0
Actually, relays are great. Their Ron:Roff ratio, isolation, breakdown
voltage, signal bandwidth, and cost per watt switched can't be beat.
Too bad they're slow and not very reliable.

Reeds are a special disappointment. They're ideal for lots of things
like analog multiplexing of nasty signals, but they never come
anywhere close to their claimed lifetimes.

John
 
J

John Fields

Jan 1, 1970
0
Actually, relays are great. Their Ron:Roff ratio, isolation, breakdown
voltage, signal bandwidth, and cost per watt switched can't be beat.
Too bad they're slow and not very reliable.
 
F

Fred Bloggs

Jan 1, 1970
0
John said:
---
So,

"This is on an ASIC, so I must DESIGN the circuit,NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip."

should really have read more like:

"This is on an ASIC, and I don't know how to DESIGN the circuit, so
any FREE help would be appreciated."

Plus the elementary nature of the question makes it more appropriate for
s.e.b...
 
J

John Larkin

Jan 1, 1970
0
Yeah, everybody but Fred should go to s.e.b. He's the only one smart
enough to post here.

John
 
J

James Beck

Jan 1, 1970
0
Don't like the attitude, huh? Too bad.
Don't like the dotsig, huh? Also too bad.

Think you've got something to say? You don't, but dumbfucks like you
don't seem to be able to come to that realization without some kind of
outside help, so here it is:

You're an ignorant son of a bitch and you have nothing important to
contribute to this group (sed). That is, out of nine posts only three
were on topic (one only marginally) and the rest were all off-topic,
inane garbage. Why don't you take a hike over to alt.cocksuckers,
where I'm sure you'll find a more appreciative audience.
WAAAAHHHHHHHH, SNIFF,SNIFF.......
Boy, you sure showed me.
Well, I'm over it. How about you?

Jim
 
C

Chris Cheney

Jan 1, 1970
0
Well, I just sort of figured that there aren't a whole lot of
different ways to connect two signals to the inputs of a d-type
flipflop.

John

Credit where it's due: it's John's D-flop as my post was in response to his
(though I didn't actually quote what he had written) - I just spelt out the
details; anyway, it's a well-known technique - at least to digital guys :).
Regards to you both. Chris
 
T

Tim Shoppa

Jan 1, 1970
0
This is on an ASIC, so I must DESIGN the circuit

If you have access to the guts of the T-flop cells, you can initialize
them to your desired phasing just by injecting the right currents on
the bases at power-up initialization.

In MSI TTL I used to see a similar trick done, but since the guts of
the cells were not available it used a significantly ruder method of
pulling the outputs to the desired "zero" states at power up through
some NPN transistors. Different manufacturer's chips responded
differently to this "initialization", of course some let their smoke
out :).

Tim.
 
J

Jim Thompson

Jan 1, 1970
0
If you have access to the guts of the T-flop cells, you can initialize
them to your desired phasing just by injecting the right currents on
the bases at power-up initialization.

In MSI TTL I used to see a similar trick done, but since the guts of
the cells were not available it used a significantly ruder method of
pulling the outputs to the desired "zero" states at power up through
some NPN transistors. Different manufacturer's chips responded
differently to this "initialization", of course some let their smoke
out :).

Tim.

I have access to all the guts... I designed them ;-) My problem is
typical... customer has extreme power constraints, and I, personally,
am leery of one-time reset-on-application-of-power situations,
particularly in a noisy consumer-product environment. My preference
is to use self-resetting circuits that "know" that they're
out-of-kilter and get themselves back into rhythm automatically. Thus
my latching (pardon the pun) onto the John/Chris D-flop "sampler" that
tells me where I am phase-wise.

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
I have access to all the guts... I designed them ;-) My problem is
typical... customer has extreme power constraints, and I, personally,
am leery of one-time reset-on-application-of-power situations,
particularly in a noisy consumer-product environment. My preference
is to use self-resetting circuits that "know" that they're
out-of-kilter and get themselves back into rhythm automatically. Thus
my latching (pardon the pun) onto the John/Chris D-flop "sampler" that
tells me where I am phase-wise.

...Jim Thompson


I doubt that a powerup reset would organize your phase relationships
here.

We had a similar problem a few years ago, on the NIF timing thing. We
had a 77 MHz biphase data stream and a 155.52 MHz (OC-3 rate)
recovered clock. Since data recovery was ambiguous (depended on clk/2)
we built in an OOPS counter that eventually decided we were at the
wrong phase and XORd the recovery clock.

John
 
J

Jim Thompson

Jan 1, 1970
0
The problem...

Running from a 2.2 GHz clock and squeezing power, I'm using T-flops
(toggle-flops).

I DIV2 on positive edge to get 1.1GHz
I also DIV2 on negative edge to get 1.1GHz but shifted +/- 90°

Continuing with the dividing I get down also to...

137.5MHz
and 137.5MHz, angle +/- 90

I want to mix the 1.1GHz and 137.5MHz signals to get either 1.2375GHz
or 962.5MHz in a image-reject mixer

The snag...

The sum/difference depends on phasing of each component, but, since
each of the final components started out from toggle flops the final
sign of the 90° is unknown.

Anyone have clever ideas to determine whether each component is + or -
90° ??

If I can determine phase I can flip to the correct phase thru a PECL
inverter.

If I can solve this then the system can simply call for high or low
sideband and be assured its the right one.

Right now it's random :-(

This is on an ASIC, so I must DESIGN the circuit, NOT buy something
off-the-shelf which consumes more power than this whole WiFi chip.

...Jim Thompson

See...

Newsgroups: alt.binaries.schematics.electronic
Subject: Problem Solution for S.E.C Posting - SidebandFix.pdf
Message-ID: <[email protected]>

Two D-flops, "WHOSFIRST", plus logic, "FLIPPER", convert commanded
"SIDEBAND" to "SBINT", providing correct sideband selection
irrespective of incoming phasing of quadrature signals 1056MHZ and
132MHz.

Thanks John and Chris!

...Jim Thompson
 
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