M
Michael Brown
- Jan 1, 1970
- 0
I'm slowly moving forward on my frequency counter design (simple counter +
TAC for partial cycles, giving one readout per second). I've decided to go
with a CPLD coupled with an ADC, currently looking at a XC9572XL and an
ADCS7476 respectively. I've taught myself enough Verilog to get a working
design using ISE Webkit - I use a serial protocol used for getting timing
information and firing calibration events, and passing through the results
from the ADC. All in all requires very few external components.
I have two questions, the first regarding the TAC part. First is whether I
should use a constant current source or a constant voltage source to charge
the capacitor. The nonlinearaties from the constant voltage source can be
dealth with through postprocessing by the microcontroller (which needs to be
done anyhow), and high-stability constant voltage sources are easy to
acquire. A constant current source would AFAIK be significantly more
complex. However I may be missing something - is it actually rather easy to
build a stable constant current source?
The basic schematic looks like:
VConst
|
|
/
Start -----|
\
|
|
|
|
/
Stop -----|
\
|
|
|-------- To ADC
|
---
---
|
|
|
GND
Both transistors being NPN. Stop is initially held high, and Start is
brought high at the start of the measurement period. At the end of the
measurement period, Stop is brought low. Soon afterwards, the ADC
measurement is made. After the ADC measurement, Start is brought low and
Stop is brought high again. The time between the start and stop pulses is
anywhere from 0 to 375 ns, and the time between the stop pule and the next
start pulse is in the order of 200 ms. I went for this dual-transistor
layout with the intention of tuning the Start transistor for a sharp rising
edge and the Stop transistor for a sharp falling edge. However, I'm not
exactly sure of the best way to do either of these For the falling edge,
I was guessing that I would hold the transistor just outside of saturation,
then use the stop signal (through another transistor) to yank the base to
ground as fast as possible. However, would this generate a noisy voltage
drop across the Stop transistor? I couldn't find much information on
increasing rising edge performance, so any tips/links regarding this would
be appreciated. Alternatively, if there's some other topology that is
better, I'm open to suggestions.
The second main question is with regards to sourcing parts. The only
Australia-local source for CPLDs that I can find is RS components, who sell
them at insanely high prices compared to what they cost from US stores. Are
there any places in Australia who charge reasonable prices for CPLDs, or is
it worthwhile to simply to batch things up and do an order from Digikey?
TAC for partial cycles, giving one readout per second). I've decided to go
with a CPLD coupled with an ADC, currently looking at a XC9572XL and an
ADCS7476 respectively. I've taught myself enough Verilog to get a working
design using ISE Webkit - I use a serial protocol used for getting timing
information and firing calibration events, and passing through the results
from the ADC. All in all requires very few external components.
I have two questions, the first regarding the TAC part. First is whether I
should use a constant current source or a constant voltage source to charge
the capacitor. The nonlinearaties from the constant voltage source can be
dealth with through postprocessing by the microcontroller (which needs to be
done anyhow), and high-stability constant voltage sources are easy to
acquire. A constant current source would AFAIK be significantly more
complex. However I may be missing something - is it actually rather easy to
build a stable constant current source?
The basic schematic looks like:
VConst
|
|
/
Start -----|
\
|
|
|
|
/
Stop -----|
\
|
|
|-------- To ADC
|
---
---
|
|
|
GND
Both transistors being NPN. Stop is initially held high, and Start is
brought high at the start of the measurement period. At the end of the
measurement period, Stop is brought low. Soon afterwards, the ADC
measurement is made. After the ADC measurement, Start is brought low and
Stop is brought high again. The time between the start and stop pulses is
anywhere from 0 to 375 ns, and the time between the stop pule and the next
start pulse is in the order of 200 ms. I went for this dual-transistor
layout with the intention of tuning the Start transistor for a sharp rising
edge and the Stop transistor for a sharp falling edge. However, I'm not
exactly sure of the best way to do either of these For the falling edge,
I was guessing that I would hold the transistor just outside of saturation,
then use the stop signal (through another transistor) to yank the base to
ground as fast as possible. However, would this generate a noisy voltage
drop across the Stop transistor? I couldn't find much information on
increasing rising edge performance, so any tips/links regarding this would
be appreciated. Alternatively, if there's some other topology that is
better, I'm open to suggestions.
The second main question is with regards to sourcing parts. The only
Australia-local source for CPLDs that I can find is RS components, who sell
them at insanely high prices compared to what they cost from US stores. Are
there any places in Australia who charge reasonable prices for CPLDs, or is
it worthwhile to simply to batch things up and do an order from Digikey?