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Technical question on Floppy Disk circuits

JW150

Mar 23, 2017
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i have been trying to figure out one aspect of floppy disk reads, related to an old industrial machine I service. The floppy circuit is a generic one, so this question doesn't require any knowledge of the machine. Nowhere have I found the answer, so it must be either something simple that is assumed everybody knows, or it is extremely technical. The question is this:

Since DD and HD 3-1/2 inch disks spin at the same speed, and because data is twice as dense on an HD disk as a DD disk, the frequency, or rate, of the data is twice that of DD. But the circuit designs I looked at appear to already know the frequency of the data. For example, one circuit had a block which introduced a "1/4 period delay" to the Read Data. But that "1/4 period" will be twice as long for DD decoding as HD decoding, correct?

So how can the FDC, or data separator, or PLL, or whatever know which type of disk (DD or HD) is in the drive sending data, so it can produce the correct data window for the Read Data pulses?

It's not a signal from the floppy drive, I am fairly certain of that. It's done on the FDC-side of the interface.

I've seen old posts on this site from folks who really understood floppy electronics; is there anyone left?

Thanks in advance. Please tell me if there is a better forum on which to pose this question.
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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The FDC probably looks at the data rate coming from the head to determine what sort of disk it is.
 

Harald Kapp

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First of all this document may give you good background information.

In the description of this data separator you'll find on page 9 the following statement:
An additional block not shown here, but used on the DP8473 is the filter selection logic. This logic is used to select different filters for different data rates. The description and use of this circuitry is described in section 5.3.
Chapter 5.3 on page 24 starts with
5.3 DP8473 Filter Switching Design Considerations Due to the desire to handle multiple data rates, the DP8473 incorporates on-chip data rate selection logic, and also filter switching logic. In this section we will discuss how this logic works and how to design a set of filters to maximize performance at various combinations of data rates.
And then goes into the details of designing the filters. This chapter is about the filters for the PLL, but the same logic that switches between filters can switch between different delay lines to accomodate the 1/4 period phase shift elsewhere.
 
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