V
vlsi99
- Jan 1, 1970
- 0
A bus interface is an output only from a chip at 50 MHZ , 3.3V
LVTTL. The target unit receives this data. I heard of some methods
used to adjust voltage thresholds and timing on the target based on a
comparison of specific test patterns. If the test patterns fails,
adjustments to thresholds on timing are made until the comparison is a
match.
The bus signals need to get to an FPGA in the target. Specifically in
hardware, what techniques have people used to accomplish this ? Can it
be done directly in the FPGA or should it be some special buffer or
analog circuit to make this adjustments?
thank you
Paul
LVTTL. The target unit receives this data. I heard of some methods
used to adjust voltage thresholds and timing on the target based on a
comparison of specific test patterns. If the test patterns fails,
adjustments to thresholds on timing are made until the comparison is a
match.
The bus signals need to get to an FPGA in the target. Specifically in
hardware, what techniques have people used to accomplish this ? Can it
be done directly in the FPGA or should it be some special buffer or
analog circuit to make this adjustments?
thank you
Paul