Angmor said:
I've been staring at a transmission gate circuit for a while trying to
figure out how it works and I'm not making any progress. The problem
we have (yes, it's a homework problem) is to determine the on
resistance for the specific gate we've been given. The circuit diagram
is basically just an nmos and a pmos connected in parallel. The input
side (I know they're interchangable) is set to 5V and both of the fets
are on (5v & 0v gate for n/p, respectively). No output voltage is
given. I've searched for a while on google trying to find helpful
information, but all I can find is that the input signal is supposed to
pass through to Vout so that Vout is almost equal to Vin.
My question is... How can I determine the output voltage? I can't
determine the transistor mode or currents without the output voltage,
and if I can't do that I cannot determine the on resistance. I am not
asking for an answer to my problem, I would just like a nudge in the
right direction if possible. This problem is driving me crazy.
As with most non-linear, it requires somewhat of a leap of faith. We have
to make an assumption about the behavior of the circuit, so lets assume
the book is right. If the output follows the input, then essentially by
definition Vds is going to be very small. The point of putting 5V and 0V
on the gate is to maximize Vgs, therefore its likely that (Vgs-Vth)>Vds.
Bear in mind that you have a complimentary setup here. If the input
voltage were very high (say 4.8V), then Vgs-Vth on the NMOS may actually
be negative, but in the same instance for the PMOS it will be very large.
So using complimentary transistors should keep one of the transistors
in the linear region at all times.
for linear region: Ids=Beta((Vgs-Vth)*Vds-Vds^2/2)
Now, consider on resistance is Rds. R=dV/dI.
it is probably easier to take dI/dV and invert. We get 1/(Beta*((Vgs-Vth)
- Vds)) If we assume Vds is small, then that term drops out and we see
that the resistance is almost completely dependent on Beta*(Vgs-Vth).
Now, what happens if your input voltage gets very high or low... Well,
you first go into saturation, and then cutoff. The standard simple models
don't work well in cutoff, so we'll just say the resistance is infinite
there. In the case of saturation Ids=Beta/2*(Vgs-Vth)^2*(1+Lambda*Vds)
So now we have 1/(Beta/2*(Vgs-Vth^2)*Lambda). While, t-gate transistors
are typically quite small to minimize capacitance, the lambda is still
likely pretty small compared to unity, so the resistance of that
transistor goes way up. At the same time, the complimentary transistor is
likely to be on pretty hard, so when you put them in parallel the
saturated transistor's contribution to overall resistance is fairly small.
Now, what if the books statement was wrong. Well, in order to have a
substantial Vds you'd have to be loading the t-gate quite heavily compared
the Rds you calculated above. At some point as you increase the load
(decrease the load's resistance to ground), the Vds will keep growing and
they will become saturated. At that point, the circuit starts working
poorly. But now that you know how T-gates work, you should be able to
design them such that you don't allow Vds to get large, hence making them
work much less effectively.
As for the other people who made some claims such as:
1) Drain and Souce aren't interchangable.... Thats absurd, of course they
are. Transistors are four terminal devices, and the source and drain are
completely interchangable. In the case of an N-MOS transistor the source
is whichever terminal is at a lower voltage, and in the case of a P-MOS
its whichever terminal is at a higher voltage. In the case of some
discrete transistors, in order to minimize pin count, they tie the bulk to
the source internally, thereby making it a 3 terminal device and making it
non-symmetric. However, that doesn't mean that the transistor terminals
aren't interchangable, just some packages aren't.
2) Saturation is only useful for semiconductor physics?! How the heck do
you think people make current mirrors? With MOSFETS in triode? Get real,
a transistor is a transistor, its not a switch, or a resistor, or anything
else. They are wonderful devices which can be operated in a number of
different regions and be used for many different things.
3) Joe's claims that digital circuits spend most of there time in linear
or cut-off region and only transition through saturation is completely
correct. He didn't mix up saturation and linear. The problem arises
because most people don't understand what saturation and linear region of
a MOSFET really mean. They describe e-field configurations on a MOSFET,
not how "on" a device is or such.