J
Joerg
- Jan 1, 1970
- 0
Hi SioL,
with a ration of 1:2 or a bit higher. The best results require a
trifilar winding where you twist three wires, wind that bundle around a
core and wire it up so the secondary towards the FET has two in series.
But watch out that the FET gate can tolerate the resulting pulse
amplitude of four times the logic level with a healthy margin. You don't
want to pulse a FET with an abs max Vgs of 20V right smack at 20V. The
goal is to transit through the threshold region of the FET as fast as
possible but not run it 'into the red'. When it's all working as desired
measure carfully with a scope to make sure there are no spikes and other
adversities that could shorten the life of the FET or the driver.
Then there is the trick of running inverted and non-inverted into the
primary and get twice the logic level out of a secondary. This only
requires bifilar winding. You could take a CAT-5 pair, twist it a bit
more, about 2 twists every inch or so. But be careful, these drivers
must be in 100% transition time sync or they might blow out. That is
less easy than it seems to be.
Mostly I just used 43 material because I have lots in the lab. This is
also the material most popular for EMI remedies, the cores you slip over
offending cables. For pulsing a FET you only need a very small core 1/4"
or so. Nowadays I often need my glasses to wind these.
To try it out use a large ferrite bead that you find in the box, or one
of those six-holer 'VK200 style' cores. A really good source on how to
wind bifilar and trifilar is the ARRL Handbook. It's a good investment
anyway.
The bottomline is that 5V logic can't directly drive high speed pulser
FETs well enough, no matter what the marketing folks say about the FET.
With 3.3V logic there is not a chance. You need a higher gate drive.
Regards, Joerg
Sometimes just by winding primary and secondary on top of each other,Hmm, this sounds interesting. How exactly did you do this toroid part?
with a ration of 1:2 or a bit higher. The best results require a
trifilar winding where you twist three wires, wind that bundle around a
core and wire it up so the secondary towards the FET has two in series.
But watch out that the FET gate can tolerate the resulting pulse
amplitude of four times the logic level with a healthy margin. You don't
want to pulse a FET with an abs max Vgs of 20V right smack at 20V. The
goal is to transit through the threshold region of the FET as fast as
possible but not run it 'into the red'. When it's all working as desired
measure carfully with a scope to make sure there are no spikes and other
adversities that could shorten the life of the FET or the driver.
Then there is the trick of running inverted and non-inverted into the
primary and get twice the logic level out of a secondary. This only
requires bifilar winding. You could take a CAT-5 pair, twist it a bit
more, about 2 twists every inch or so. But be careful, these drivers
must be in 100% transition time sync or they might blow out. That is
less easy than it seems to be.
Mostly I just used 43 material because I have lots in the lab. This is
also the material most popular for EMI remedies, the cores you slip over
offending cables. For pulsing a FET you only need a very small core 1/4"
or so. Nowadays I often need my glasses to wind these.
To try it out use a large ferrite bead that you find in the box, or one
of those six-holer 'VK200 style' cores. A really good source on how to
wind bifilar and trifilar is the ARRL Handbook. It's a good investment
anyway.
The bottomline is that 5V logic can't directly drive high speed pulser
FETs well enough, no matter what the marketing folks say about the FET.
With 3.3V logic there is not a chance. You need a higher gate drive.
Regards, Joerg