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VHDL coding for AES-128

manish29101991

Apr 12, 2013
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Apr 12, 2013
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Hello everyone..!!
Can anyone please provide me with the VHDL coding for AES-128(Advanced Encryption Standard for 128 bit key length). Encryption+decryption both. Its urgent. Please help the needy.
Mail me the coding at my gmail id:
[E-mail removed]
Heartiest thanks in advance.
 
Last edited by a moderator:

Harald Kapp

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Nov 17, 2011
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Why is it urgent? Is it homework you've put on the back burner for too long? Then it should be placed in the homework section.
What have you done so far?
Do you have at least the skeleton of the code?
 

manish29101991

Apr 12, 2013
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Apr 12, 2013
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Its my graduation project. I m running short of time. Block diagram should consist of a single block having 5 inputs- 128 bit binary plain/cipher text , 128 bit binary key, clock, reset & a user selection signal for performing either encryption or decryption(0 for encrypt & 1 for decrypt) and 1 output-128 bit binary cipher /plain text.
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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Jan 21, 2010
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Sounds like you've done nothing so far.

I implemented DES for a project in my final year at university.

I didn't leave it until the last moment though.
 

manish29101991

Apr 12, 2013
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i have started the project but i got stuck in mix column and add round key stage in encryption of data. how to proceed ?
 
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