I'm supposing you are referring the tendency of the "A" series CMOS
components (4000 series chips) to latch up when power is applied.
This is due to a parasitic SCR inherent in its design. Looking through
the layers, there would be a PNPN structure. If this latches on, there
would be a destructive current flow causing the chip to self destruct.
If it is not clear from the document, then the document is incomplete.
At a minimum, contact the individual who wrote the document;
better yet, have him re-write it so that things are clear.
Fuzzy specs benefit no one.
This was my interpretation of the prose:
Upon starting a Master Device, all slave devices are enabled.
I sounds like Jasen interpreted the sequence of events correctly: