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Why can't cache memory size be bigger?

Tristan369

Oct 29, 2020
32
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Oct 29, 2020
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I've read a few answers online to this question, and the answer seems to be that the way in which we access memory from cache is slower the bigger the cache is.

But then why don't we just access memory differently? And how exactly is the memory accessed in cache anyway?

Why can't you just have, say, a 64-bit bus with a register at every address? You simply access the memory by entering the right address into the bus, and each register has some logic on the bus lines to determine whether it is on or off. Any register could be accessed in a single clock cycle no matter how large the memory is, right?

The only thing I can think of is maybe the physical size of the memory and the speed of electrons are also a limitation? Or I just don't understand why my idea wouldn't work. Thank you.
 
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