# Why OR gates?

E

#### eromlignod

Jan 1, 1970
0
Hi guys:

Here's just a simple, silly question from a non-EE that probably has a

If I have several TTL logic outputs that I want to "OR" together, so
that any of these will drive the output of the OR gate, why can't I
just connect the output wires together physically, merging them into
one wire, without using the gate?

One reason I can think of is that it avoids the case where two
connected wires are high at the same time. But if I ensure that this
cannot happen due to my upstream design (like a decoder), do I still
have to use the OR, or can I merge the outputs?

Don

T

#### Tam/WB2TT

Jan 1, 1970
0
eromlignod said:
Hi guys:

Here's just a simple, silly question from a non-EE that probably has a

If I have several TTL logic outputs that I want to "OR" together, so
that any of these will drive the output of the OR gate, why can't I
just connect the output wires together physically, merging them into
one wire, without using the gate?

One reason I can think of is that it avoids the case where two
connected wires are high at the same time. But if I ensure that this
cannot happen due to my upstream design (like a decoder), do I still
have to use the OR, or can I merge the outputs?

Don
If you tie the outputs of two TTL gates together, and one output is a 1 and
the other a 0, you end up with a short corcuit between VCC and ground
through the gates. For a 74Fxxx, for instance, you will draw about 100 ma,
and the resultant output will be neither a 1 or a 0.

Tam

E

#### eromlignod

Jan 1, 1970
0
If you tie the outputs of two TTL gates together, and one output is a 1 and
the other a 0, you end up with a short corcuit between VCC and ground
through the gates. For a 74Fxxx, for instance, you will draw about 100 ma,
and the resultant output will be neither a 1 or a 0.

OK. I knew it was something stupid. I was thinking that gate outputs
are high-impedance, but it's the inputs that are hi-Z. Duh.

What I'm trying to do it select one of three inputs without using a
lot of chips, or wasting a lot of gates. I know that there are MUX's,
like the 74153 that have dual 2 to 4 selectors, but I hate to waste
the second MUX. I was hoping to use three AND gates with 3 enable
lines, but then if I need an OR gate, that's another chip...probably a

Don

M

#### Michael Black

Jan 1, 1970
0
eromlignod" ([email protected]) said:
Hi guys:

Here's just a simple, silly question from a non-EE that probably has a
If you'd asked where this belongs, sci.electronics.basics I'd take
a shot at answering it. But since you can't bother to find the right
newsgroup, I won't.

This is not a design question, it doesn't belong in a newsgroup about
design.

Michael

F

#### Fred M

Jan 1, 1970
0
If you'd asked where this belongs, sci.electronics.basics I'd take
a shot at answering it. But since you can't bother to find the right
newsgroup, I won't.

This is not a design question, it doesn't belong in a newsgroup about
design.

Michael

Well, sorta. TTL inputs are medium-high (Z loading on an output is a
factor based on number of inputs driven).
CMOS inputs are quite high (only distributed capacitance of multiple
traces/inputs is a rise/fall time factor).

Fred

F

#### Fred M

Jan 1, 1970
0
Well, sorta. TTL inputs are medium-high (Z loading on an output is a
factor based on number of inputs driven).
CMOS inputs are quite high (only distributed capacitance of multiple
traces/inputs is a rise/fall time factor).

Fred

Oops, sorry Michael - meant to reply to author.

F

#### Fred M

Jan 1, 1970
0
OK. I knew it was something stupid. I was thinking that gate outputs
are high-impedance, but it's the inputs that are hi-Z. Duh.

What I'm trying to do it select one of three inputs without using a
lot of chips, or wasting a lot of gates. I know that there are MUX's,
like the 74153 that have dual 2 to 4 selectors, but I hate to waste
the second MUX. I was hoping to use three AND gates with 3 enable
lines, but then if I need an OR gate, that's another chip...probably a

Don

Well, sorta. TTL inputs are medium-high (Z loading on an output is a
factor based on number of inputs driven).
CMOS inputs are quite high (only distributed capacitance of multiple
traces/inputs is a rise/fall time factor).

Fred

G

#### GregS

Jan 1, 1970
0
Hi guys:

Here's just a simple, silly question from a non-EE that probably has a

If I have several TTL logic outputs that I want to "OR" together, so
that any of these will drive the output of the OR gate, why can't I
just connect the output wires together physically, merging them into
one wire, without using the gate?

One reason I can think of is that it avoids the case where two
connected wires are high at the same time. But if I ensure that this
cannot happen due to my upstream design (like a decoder), do I still
have to use the OR, or can I merge the outputs?

Don

DTL is what you seem to want to do. You can add steering diodes.

greg

R

#### Robert Latest

Jan 1, 1970
0
eromlignod said:
If I have several TTL logic outputs that I want to "OR" together, so
that any of these will drive the output of the OR gate, why can't I
just connect the output wires together physically, merging them into
one wire, without using the gate?

Of course you can. It's a very common construct called "Wired OR".
One reason I can think of is that it avoids the case where two
connected wires are high at the same time.

No problem with open-collector outputs. Otherwise just add some diodes.
cannot happen due to my upstream design (like a decoder), do I still
have to use the OR, or can I merge the outputs?

Since you are using TTL, and since TTL usually has OC outputs (but do check
the datasheets of your chips to make sure), there is no problem. With
push-pull outputs (such as CMOS, like the 40xx or 74HCxx series) what you
have in mind is not only bad design, but it simply won't work at all.

robert

J

#### John Barrett

Jan 1, 1970
0
eromlignod said:
OK. I knew it was something stupid. I was thinking that gate outputs
are high-impedance, but it's the inputs that are hi-Z. Duh.

What I'm trying to do it select one of three inputs without using a
lot of chips, or wasting a lot of gates. I know that there are MUX's,
like the 74153 that have dual 2 to 4 selectors, but I hate to waste
the second MUX. I was hoping to use three AND gates with 3 enable
lines, but then if I need an OR gate, that's another chip...probably a

Don

diode-or just make sure they dot drop the voltage below TTL threshold
(which is why they are not generally used for OR gates)

---|>|---|
|-------
---|>|---|

B

#### [email protected]

Jan 1, 1970
0
Of course you can. It's a very common construct called "Wired OR".

No problem with open-collector outputs. Otherwise just add some diodes.

Since you are using TTL, and since TTL usually has OC outputs (but do check
the datasheets of your chips to make sure), there is no problem. With
push-pull outputs (such as CMOS, like the 40xx or 74HCxx series) what you
have in mind is not only bad design, but it simply won't work at all.

This is badly phrased. There are TTL parts with open-collector outputs
- the SN7406 - for example, and these can be used to build wired-OR
functions.

http://focus.ti.com/docs/prod/folders/print/sn7406.html

Most TTL parts have a totem-pole output which can both source current
(1 or high state) or sink current ( 0 or low state) and you shouldn't
use them for wired-ORs,

Emitter-coupled logic (ECL) uses an NPN transistor as the output
driver, and can only source current - it relies on a pull-down
resistor (usually 50R to -2V) to provide the pull-down current to
generate a low (0) output, and all ECL parts can be used to produce
wired-ORs, though it isn't a good idea if the gates being OR'd are
more than an inch (a few centimetres) or so apart.

R

#### Rich Grise

Jan 1, 1970
0
diode-or just make sure they dot drop the voltage below TTL threshold
(which is why they are not generally used for OR gates)

---|>|---|
|-------
---|>|---|

If you invert the inputs, turn the diodes around into a wired-and, and
invert the output, it achieves the same thing (by DeMorgan's theorem),
and has a better chance of working with TTL, which has strong pulldowns
but weak pullups.

Cheers!
Rich

R

Jan 1, 1970
0
T

#### Tam/WB2TT

Jan 1, 1970
0
This won't work into TTL because it leaves the input to the next stage
floating, which is a mostly ONE. If you add a pulldown of sufficiently low
value you won't be able to drive it. This basic configuration will work if
you use resistors, instead of diodes, and connect them to the base of a
transistor. Connect another resistor from collector to ground. What you have
now is a NOR gate; so, you need to invert that.
If you invert the inputs, turn the diodes around into a wired-and, and
invert the output, it achieves the same thing (by DeMorgan's theorem),
and has a better chance of working with TTL, which has strong pulldowns
but weak pullups.

Cheers!
Rich
This will work. Notice, Rich said to invert the signals. You will need a
~10K resistor from the diode outputs to VCC.

Tam

T

#### Tam/WB2TT

Jan 1, 1970
0
Richard Henry said:
I did not know that.
You didn't know that because it is NOT true.

Tam

D

#### Dan Bloomquist

Jan 1, 1970
0
Tam/WB2TT said:
This will work. Notice, Rich said to invert the signals. You will need a
~10K resistor from the diode outputs to VCC.

I would not think this reliable as the diode puts you at the threshold
instead of in the low region.

Best, Dan.

R

#### Rich Grise

Jan 1, 1970
0
I would not think this reliable as the diode puts you at the threshold
instead of in the low region.

Eek. You're right. I guess it worked for me before because I didn't know
that, much like the bumblebee doesn't know it's impossible for him to
fly. ;-)

(I probably just lucked out on margins & stuff.)

Thanks!
Rich

S

#### Stanislaw Flatto

Jan 1, 1970
0
eromlignod said:
Hi guys:

Here's just a simple, silly question from a non-EE that probably has a

If I have several TTL logic outputs that I want to "OR" together, so
that any of these will drive the output of the OR gate, why can't I
just connect the output wires together physically, merging them into
one wire, without using the gate?

One reason I can think of is that it avoids the case where two
connected wires are high at the same time. But if I ensure that this
cannot happen due to my upstream design (like a decoder), do I still
have to use the OR, or can I merge the outputs?

Don
OK, this is your design and I won't comment on it.
But from my short (25 years plus) time spent in various designs I can
assure you one thing. Mr. Murphy is a constant companion so designing to
evade his inerference is futile (Star Trek). The problem is to ensure
that your signals don't create low-high couples, and for this you have
the OR gate as a bouncer.
Not only that, but it is a component in Boolean logic, and we love to
use math before assembly.

Have fun

Stanislaw

D

#### Dan Bloomquist

Jan 1, 1970
0
Rich said:
Eek. You're right. I guess it worked for me before because I didn't know
that, much like the bumblebee doesn't know it's impossible for him to
fly. ;-)

(I probably just lucked out on margins & stuff.)

Well, I'm only marginally right.

Best, Dan.

R

#### Richard Henry

Jan 1, 1970
0
You didn't know that because it is NOT true.

Usually when I say that in a meeting people understand it to be dead-
pan sarcasm.

However, I don't know how to inflect that in a newsgroup post.

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