S
Spehro Pefhany
- Jan 1, 1970
- 0
Hi, all:-
A bit of a long shot here, but does anyone know whether the inputs
will float on the Xilinx CPLD parts will float when power is not
applied or do they have a nasty protection structure to a supply pin?
And if so, what if I float the related Vccio pin-- will that allow the
input current to be reduced to just leakage current?
I don't see any info in what appears to be the relevant document:
http://direct.xilinx.com/bvdocs/appnotes/xapp382.pdf
Best regards,
Spehro Pefhany
A bit of a long shot here, but does anyone know whether the inputs
will float on the Xilinx CPLD parts will float when power is not
applied or do they have a nasty protection structure to a supply pin?
And if so, what if I float the related Vccio pin-- will that allow the
input current to be reduced to just leakage current?
I don't see any info in what appears to be the relevant document:
http://direct.xilinx.com/bvdocs/appnotes/xapp382.pdf
Best regards,
Spehro Pefhany