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Improvements in MRAM Capacity Allow Scaling for L4 Cache Applications

December 20, 2019 by Luke James

Improvements made in magnetic tunnel junctions have allowed a 2 MB magnetic random-access memory array to be scaled for L4 cache applications.

With major advances being made in the fields of artificial intelligence, machine learning, and the Internet of Things (IoT), more and more pressure is being placed on computing hardware developers and manufacturers to come up with solutions that can store and retrieve ever-growing amounts of data in a faster and more energy-efficient manner. 

In conventional computing systems, one of the biggest performance bottlenecks is the speed gap between processor and memory. Up until now, memory hierarchy—where memories are classified and sorted into different levels depending on speed and capability—have managed to reduce this gap. However, conventional semiconductor technology, such as static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM), is failing to keep up with current demands in energy efficiency, density, and speed.

MRAM is one alternative approach.


Magnetoresistive RAM (MRAM)

Magnetoresistive random-access memory (MRAM) is one of the possible alternatives to memory found on conventional semiconductor technology. Currently, MRAM is produced by Everspin Technologies and in 2016, companies such as GlobalFoundries and Samsung announced their own product plans for it

It is a type of non-volatile RAM that stores data in magnetic domains. While it was developed in the mid-1980s and has been poised to become the dominant universal memory standard, other memory technologies such as DRAM have more practicality and have kept MRAM in the shadows. 

The base cell of MRAM is a magnetic tunnel junction that consists of a fixed magnetic layer, a non-magnetic tunnel barrier, and a magnetic free layer. The tunnel junction’s resistance state is determined by the relative magnetization direction between the fixed and free layer, where a low (high) resistance state refers to the parallel (antiparallel) alignment of the magnetizations. 


A schematic of memory hierarchy (a) and a schematic of a magnetic tunnel junction (b).

A schematic of memory hierarchy (a) and a schematic of a magnetic tunnel junction (b). Image Credit: Nature Electronics.


As a current is driven across the junction, the magnetization of the free layer can be switched via the spin-transfer torque effect. This allows binary information to be stored as low- and high-resistance states in the tunnel junction. 


2 MB STT-MRAM Array Capable of L4 Cache Application

STT-MRAM has gained attention due to its non-volatile properties and compatibility with current semiconductor technology, alongside its fast operation speed, long-endurance, and high density.

At the 2019 IEEE International Electron Devices Meeting in San Francisco, Intel’s Juan Alzate and colleagues demonstrated a 2 MB STT-MRAM array that is capable of level 4 (L4) cache application. 

While L4 is not as fast as caches closer to the core (e.g. L1 and L2) in the memory hierarchy, it has a higher capacity. Compared with eNVM, L4 cache imposes stricter requirements such as higher density, better endurance, faster speed, and a lower bit error rate. To meet these requirements, Intel researchers optimized the process to fabricate STT-MRAM arrays.

Intel researchers improved array density so that they could place it on-chip. This requires a smaller transistor and tunnel junction size within a single memory cell. Potential complications with maximum writing and current, however, the optimized process allowed researchers to fabricate tunnel junctions with a size smaller than 55 nm. These show acceptable write error rates for array-level operation. 

Frequent operation of the L4 cache requires great endurance, however, retention time can be relaxed thanks to data scrubbing. To address read disturbance, Intel’s researchers tested the fabricated STT-MRAM arrays and reported a one second retention at 110 °C, an endurance of 1012 cycles, and an acceptable bit error rate (<10−5) for read disturbance. 

All this illustrates that such STT-MRAM arrays are ready for an L4 cache application.

The demonstration by Intel of L4 cache-ready STT-MRAM should encourage further developments on STT-MRAM for other level memory applications. Further development of it is essential for commercial products and further technological advances as current memories are quickly approaching maximum capacity.

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