Maker Pro

Intel Says that EUV is Ready but Problematic for Engineers

June 08, 2019 by Luke James

In a recent interview, Brett Turkot, director of EUV at Intel, went on record to say that their EUV lithography is ready for introduction, however, engineers will still face several challenges in using the system to make these leading chips at a high volume.

Recently, and especially in the last few months, there have been many announcements surrounding EUV lithography. Both TSMC and Samsung have made significant strides with the technology, announcing that they were ramping up 7nm nodes using EUV systems, so it was only a matter of time until Intel came out and made an announcement regarding their own progress.

Despite Intel being the pioneer of the technology over 20 years ago, they have fallen behind and are among the last of the major chip manufacturers to confirm its use.


All Systems Go... or Not

In a recent interview, Intel's EUV head, Brett Turkot, said that EUV lithography is "ready for introduction … and running in volume for technology development" despite there still existing several challenges surrounding it for engineers.

Despite not divulging if or how EUV will be used for Intel's 10nm and 7nm products, Turkot said that their room-sized systems are now fully operational and running in Intel's Portland, Oregon manufacturing site.


Image courtesy of ExtremeTech.


Although Intel is now running EUV at volume for technology development, Intel's engineers are still struggling to use it in the manufacturing of cutting-edge chips at scale.


Everything is Not as it Seems

While TSMC and Samsung may have pipped Intel to the post with their early announcements, it has been reported that TSMC's N7+ is only using EUV for four metal layers. This means that the use of double patterning is still required, using immersion steppers for some metal layers.

In response, a TSMC spokesperson said that "We indeed deploy double patterning in many layers. ... The decision to use immersion double patterning versus EUV is based on a number of considerations. EUV’s cost [and] maturity versus immersion definitely is important".

It's not just TSMC, though: Samsung has declined to comment on how they are using EUV, too. Given that Samsung has fewer EUV tools than TSMC, they should be at most using the same number of metal layers at 7nm. The rest would be triple or even quadruple-patterned, but this is mere speculation on our part.


Image courtesy of Electronics Weekly.


So, although last, Intel's late EUV announcement should not be viewed in too much of a negative light. Similarly, TSMC and Samsung's announcements should be taken with a grain of salt.


Intel's 10nm Node is 'Ambitious'

Recently, Intel's chief engineering officer, Murthy Renduchintala, went on record to call the company's 10nm node plans as ambitious. Previously critical about Intel's 10nm efforts, he has also said that "We have humble pie to eat right now, and we're eating it, … My view on 10nm is that brilliant engineers took a risk, and now they're retracing their steps and getting it right".

To balance this, though, Renduchintala also said that chips using 10nm are now in production and a lot of good progress has been made in their work on a 7nm node, too. Given that Intel claimed in 2013 that they would be procuring chips using EUV 10nm lithography by 2015, the company is likely very pleased to finally be making progress.


What are Intel's Plans?

Returning back to Brett Turkot's interview, Turkot said that Intel has yet to decide how many metal layers it is going to use with EUV, and that deciding on the number is just as much an art as science, adding that a single EUV exposure can reduce a layer's mask count by a ratio of up to 5:1.

Furthermore, there is an inherent system reliability issue; Intel currently reports that theirs is at around 75 to 80 percent for EUV systems. This is likely unsustainable long-term, but considering Intel's current standing, acceptable.

Looking forward, it is anyone's guess what is going to happen.

"A lot of effort is going into debugging EUV, like any new platform. The whole intent has been that when it’s time for production, we can’t tell the difference—it’s a seamless transition", said Turkot.

Related Content


You May Also Like