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The EU Sponsors a RISC-V European Platform for Space and Aviation Markets

December 06, 2019 by Luke James

A new European project called De-RISC is preparing a hardware-software platform based on RISC-V for the space and aviation market. De-RISC plans to create a market-ready platform for future space and aviation applications with European technology.

Through a program partly funded by the European Union, a four-company partnership is hoping to bring free and open source silicon to the space and automotive market. 

Combining a multicore system-on-chip (SoC) by Cobham Gaisler, a leading space solutions provider, with fentISS’ space-qualified XtratuM hypervisor, Europe’s De-RISC hopes to create a market-ready platform that will power future applications in the space and aviation spaces with entirely made-in-Europe technology. 


A Europe-Wide Collaboration 

Cobham Gaisler AB, part of Cobham Advanced Electronics Solutions, is a Swedish provider of IP that supports development tools for embedded processors based on the SPARC architecture. 

fentISS, acting as project coordinator, is an advanced technology company that provides software solutions enabling critical and non-critical applications to share a common hardware platform without interfering with one another. 


De-RISC Logo

Image courtesy of De-RISC.


It is not only these two companies that have a part to play, though. 

Thanks to Barcelona Supercomputing Center’s (BSC) multicore interference mitigation techniques, the market-ready platform will offer high-performance operation with reduced interference. In the meantime, Thales SA—a major player in the global space and aviation market—will test the platform on real aerospace applications. 

Paco Gomez Molinero, CEO of fentISS and De-RISC project coordinator, said, “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications, thus contributing to the ‘Technologies for European non-dependence and competitiveness’ programme in these strategic markets,”


Limiting Interference While Preserving Performance

BSC’s multi-core inference mitigation concepts integrated into the RISC-V SoC and validated by Thales SA will become a unique feature and provide a key advantage with respect to competitors by drastically limiting interference while maintaining high-performance operation. 

The use of RISC-V will futureproof the platform thanks to ever-increasing support for the open-source instruction set architecture. The timing here is rather apt; proprietary PowerPC and SPARC architectures traditionally used in space and aviation systems are experiencing a loss of momentum. As a result, the industry cannot leverage software from commercial domains, fuelling a need to shift architectures. De-RISC will not be ported to SPARC or PowerPC architectures. 

At the end of the project, De-RISC will be a RISC-V HW/SW platform that can be implemented in application-specific standard products and FPGAs. This provides customers that can adapt their choice of implementation technology based on specific requirements with an edge over competitors. 


Free from U.S. Export Restrictions

One of the less-talked-about key positives with the De-RISC project is that it will be free from export restrictions placed by the U.S. on selected high-tech items. Most importantly, De-RISC’s core platform will not be subject to U.S. influence despite building on RISC-V.

Commenting on the fact that most of today’s biggest and most exciting products use U.S. technology, and thus subject to U.S. export control, Molinero said, "De-RISC’s IP core platform and [its] software will not be subject to any US regulatory influence by building on RISC-V."


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