GloFo (GlobalFoundries) has qualified Synopsys' Fusion Design Platform for its 12nm FinFET (fin-field effect transistor) process. Qualification includes leading products Design Compiler NXT, IC Compiler II, PrimeTime, and StarRC.
Earlier this month, Synopsys announced that GlobalFoundries (GF) had qualified the former’s Fusion Design Platform for its 12 nm leading-performance (12LP) FinFET platform. This platform is optimised for the high-performance and low-power requirements of cloud computing, AI, and mobile system on chip (SoC).
The 12 nm production-ready flow is based on the silicon-proven RTL-to-GDSII 12LP foundry reference flow. It also incorporates Synopsys' Advanced Fusion technologies for the best quality of results and time-to-results (QoR and TTR) in FinFET designs.
Vice president of Engineering and Design Enablement at GlobalFoundries, Richard Trihy, stated:
“We want to ensure that GF customers that want to use our differentiated FinFET technology for their next-generation chip designs have the easiest possible path to implementation and production.”
"GF's 12LP FinFET platform delivers a 10 percent improvement in logic density and more than a 15 percent improvement in performance. This, combined with the QoR and TTR advantages provided by the Synopsys Fusion Design Platform, enable our mutual customers to differentiate their products in artificial intelligence, cloud computing, and high-end consumer SoCs."
Diagram detailing the functions of the Fusion Design Platform. Image Credit: Synopsys.
Leading TTR in FinFET Designs
Some of the key tools and technologies of Synopsys' Fusion Design Platform include:
IC Compiler II place-and-route with Advanced Fusion Technology: fully-automated flow with comprehensive GF 12LP rules support. Deployment of advanced legaliser, pin density-aware placement, total power optimisation, logic restructuring, and the Engineering Change Order (ECO) closure
Design Compiler Graphical and Design Compiler NXT RTL synthesis: advanced power, performance, and area (aka PPA) optimisations, congestion reduction, pin access-aware optimisation, tight correlation, and physical guidance for IC Compiler II
IC Validator physical sign-off: physical sign-off, including design rule checking DRC), layout versus schematic (LVS), and Fill. Innovative Explorer DRC and Live DRC technologies for enhanced productivity
PrimeTime timing sign-off: advanced variation modelling for low voltages, and enhanced ECO technologies with support for new physical design rules
StarRC extraction signoff: advanced modeling to handle the complexity of FinFET devices, as well as a common technology file for parasitic extraction consistency from synthesis, to place-and-route, to sign-off
Synopsys, Inc. is the Silicon to Software partner for innovative companies that develop the products and software applications that consumers and industry rely on every day. It is the world's 15th-largest software company and has a long and rich history of being a global leader in electronic design automation.