This article explains how to implement a high-speed 6-Bit asynchronous Binary Rate Multiplier (BRM) using the PIC16F13145 Microcontroller’s built-in Configurable Logic Block (CLB), enabling efficient hardware-based frequency scaling for applications such as digital waveform synthesis, precision pulse generation, and time-domain signal modulation.
Within, we will explore the practical steps for using the MPLAB Code Configurator (MCC) Configurable Logic Block (CLB) Synthesizer to implement the counter and logic necessary for both 4-bit and 6-bit Binary Rate Multipliers (BRMs). The 4-bit BRM configuration enables fractional frequency division by N/16, where N ranges from 1 to 15, while the extended 6-bit BRM supports division by N/64, where N ranges from 1 to 63. These configurations allow the output frequency to be finely scaled between 1/16 and 15/16 or 1/64 and 63/64 of the input frequency, depending on the resolution selected. Such control is ideal for applications requiring digital waveform synthesis, precise timing control, or pulse density modulation. The implementation involves constructing a synchronous counter (either 4-bit or 6-bit, as required) and logic gates that compare the counter output to the programmed value of N, gating the input clock accordingly. The MCC CLB Synthesizer streamlines this process by providing a graphical interface to configure LUTs, counters, and combinatorial logic, and allows assignment of internal signals to GPIO output pins for external integration and debugging.
