This design uses the PIC16F13145 Configurable Logic Block (CLB) to emulate the behaviors of the 4021 shift register and replace legacy hardware to implement a custom NES joypad design.
Abstract
A PIC16F13145 was used to interface directly with a Nintendo Entertainment System controller port with its Configurable Logic Block (CLB). The CLB allows a single PIC microcontroller to replace a legacy shift register as an interface device and enable software-based enhancements to controller designs, such as a turbo mode implemented in software.
Implementation
This design uses the PIC16F13145 Configurable Logic Block (CLB) to emulate the behaviors of the 4021 shift register to implement a custom NES joypad design. The NES uses a high-speed, SPI-like communications protocol to poll inputs from its joypads, requiring the joypad hardware to decode pulses only several hundred nanoseconds in width. As the PIC1613145 cannot interface directly with the NES joypad interface due to the strict timing requirements of the system, the CLB is used to implement a hardware peripheral to allow the MCU to communicate with the NES. The CLB is used to swiftly process input signals from the NES controller port and use them to generate an output signal in this application. The PIC16F13145 polls inputs from an MCP23017 I/O expander over I2C and is able to pass the button values along to the CLB through the software input register to be read by the NES through the Data output. A turbo feature, common in enhanced NES controllers, is implemented in software to demonstrate the utility of combining a microcontroller with reconfigurable logic.
This controller has been tested and is compatible with original NES hardware, a software-based emulator (Hyperkin Retron 1 A/VY, and an FPGA-based emulator (RetroUSB AVS).
A counter-multiplexer design is implemented by the CLB to emulate the behaviors of the 4021 shift register. The 4021 is a parallel-load shift register in which each individual flip flop may be set or reset individually when a latch signal is applied. However, the CLB cannot implement this circuit due to design limitations and so a compatible design was created. When the NES is polling button values from the 4021, it sends a Latch pulse to lock in the button data and then sends Clock pulses to shift the data out from the shift register, reading it in through its Data input line bit by bit. This design uses a Configurable Logic Cell-generated clock derived from NES control signals (Latch and Clock) to synchronize the counter with the Latch signal and determine the number of clock cycles to generate the correct output corresponding to the button being polled. In this design, CLB is capable of outputting the correct value for each button independently of the PIC16F13145 core, although the PIC16F13145 must refresh the button inputs to the CLB every 10 ms during its I2C poling function to beat the 60 Hz / 16.6 ms refresh rate of the original system.
A printed circuit board was designed to interface a set of push buttons to an I2C interface expander (MCP23017), which is polled by a PIC16F13145 Curiosity Nano evaluation board. The PIC16F13145 Curiosity Nano is then routed directly to the NES controller port, by which it is powered. The Latch and Clock signals from the controller port are used by the CLB to generate outputs through the CLB Data output, which is routed to be read by the NES.
The PIC16F13145 firmware implements a polling function in which it polls the button values over I2C every 10 ms and updates the CLB through the software register, using Timer 0's overflow interrupt for this purpose. A software oscillator toggles an oscillator bit every 66 ms to implement a turbo function, using Timer 1's overflow interrupt. This turbo function can be set using a DIP switch on the PCB and allows for independent configuration of this feature for the A and B buttons. This turbo function defeats software debounce algorithms used by software to ignore a held button by toggling its state repeatedly while pressed; this feature was very popular with platformers and shooters involving rapid projectile fire.
Demonstration video
Images
Software flowchart for PIC16 program implementing controller
3D model of controller hardware designed for this project
Configurable Logic Block Synthesizer diagram describing design used to interface PIC16 with NES port through CLB
Logic analyzer diagram showing data signals generated by the CLB in response to clock and latch signals from the NES
Resources
Please read the attached PDF file for a detailed report on the design and implementation of this project. Technical products, such as source code, bill of materials, electronic schematics, Gerber files, and other technical details can be found in the report or attached ZIP files.
