This project is a real-time logic watchdog designed to supervise the command and response of a simulated circuit breaker — a small system inspired by the needs of electrical substations. Instead of using traditional software logic, I built it using the Configurable Logic Block (CLB) inside the PIC16F13145 Curiosity Nano.
WHAT IT DOES
The system detects and flags four possible logic states of a relay:
- Idle (normal, no command issued).
- Valid command and response.
- No response to a command (alarm).
- Unexpected relay trip (alarm).
It also monitors the analog voltage of the relay’s power supply. If the voltage drops below a threshold, it lights up a Low Battery LED — all through hardware logic. You can even simulate test conditions (like forcing faults or triggering alarms) via UART commands, making it a great tool for testing and diagnostics.
Prototype setup showing LED indicators and CLB inputs.
WHY IS IT COOL?
- Logic runs in hardware: The whole decision-making lives inside the CLB — no need to use CPU cycles for evaluating signals or voltages.
- Low CPU load: The processor just reads the ADC and passes some UART data. It works at ~19% load, which is awesome for low-power designs.
- Real-time response: Since the logic doesn’t depend on code execution, it reacts in just a few clock cycles.
- Great for SCADA-style supervision: It models real substation behavior with simple, safe, low-voltage components.
Live ADC monitoring showing threshold detection triggering CLB logic.
HOW THE CLB HELPED TO BRING IT TO LIFE
The CLB was the heart of this project. I used 25 out of the 32 available LUTs, packing in watchdog logic, analog voltage thresholds, UART command interpretation, and even LED control — all without using interrupts or timers.
This modular hardware logic allowed me to build a deterministic and expandable system with full separation from firmware logic. The CPU just watches while the CLB does all the thinking.
CLB Designer view with logic gates and Verilog components for fault state detection.
#include "mcc_generated_files/system/system.h"
#define RX_BUFFER_SIZE 8
int main(void)
{
SYSTEM_Initialize();
__delay_ms(100);
int16_t value;
char rxBuffer[RX_BUFFER_SIZE] = {0};
uint8_t rxIndex = 0;
uint8_t receivedNumber = 0;
printf("System ready. Enter a number (1-4) to control the CLB.\r\n");
while(1)
{
// Perform ADC conversion on analog input ANA5
ADC_SampleCapacitorDischarge();
value = ADC_ChannelSelectAndConvert(ADC_CHANNEL_ANA5);
// //printf("adc: %d", value);
// Check if data is available from UART
if (EUSART1_IsRxReady())
{
char c = EUSART1_Read();
// If the character is a digit (0–9), store it in the buffer
if (c >= '0' && c <= '9')
{
if (rxIndex < RX_BUFFER_SIZE - 1)
{
rxBuffer[rxIndex++] = c;
}
}
// If ENTER key is pressed (newline or carriage return), process the input
else if (c == '\r' || c == '\n')
{
if (rxIndex > 0)
{
rxBuffer[rxIndex] = '\0'; // Null-terminate the string
receivedNumber = (uint8_t)atoi(rxBuffer);
rxIndex = 0; // Reset buffer index
// Process only valid commands (0 to 4)
if (receivedNumber <= 4)
{
// Shift the command 8 bits to the left to occupy the upper byte of 16-bit word
uint16_t UARTcommand = (1 << 3 | receivedNumber) << 8;
// Combine the 8-bit ADC value with the 8-bit command
uint16_t bit_data = (value & 0x00FF) | UARTcommand;
CLB1_SWIN_Write16(bit_data); // Write the full 16-bit input to CLB SWIN interface
// Print message depending on the selected command
switch (receivedNumber)
{
case 0: printf("Command 0: Reserved command. Use numbers 1 to 4 only.\r\n"); break;
case 1: printf("Command 1: Simulate no response after an open command.\r\n"); break;
case 2: printf("Command 2: Simulate low battery.\r\n"); break;
case 3: printf("Command 3: Activate remote alarm.\r\n"); break;
case 4: printf("Command 4: Deactivate remote alarm.\r\n"); break;
}
}
else
{
printf("Invalid command. Use numbers 1 to 4 only.\r\n");
}
}
}
else
{
// Reset buffer on invalid character (non-digit and not ENTER)
rxIndex = 0;
}
}
}
}
A functional demonstration is attached below.
IMPACT AND HOW IT CAN BE USED
In real-world substations, this same logic can be adapted to offload processing from an RTU or work alongside it. Instead of replacing big control units, it can handle localized tasks — like validating breaker states or simulating faults for testing — fast, independently, and reliably.
Imagine integrating a few of these on the edge of a SCADA system: less network chatter, faster detection, and better diagnostics.
CLB-based logic supervisor mapped to substation monitoring concepts — a low-cost hardware co-processor for high-integrity systems.
Want to know more?
A full PDF report with schematics, Verilog logic, code and theory — plus all project files in a downloadable zip — will be attached below. If you're curious about real-time logic design, or you're working on anything related to protection systems, you might just find this useful (or at least fun to explore).
Stay curious — and keep building!
