'Low Power VLSI' :Help me to choose best domain for M.tech project

[gstekboy]

I'm Studying M.tech VLSI , as a part of my course I selected 'Low Power VLSI' as my project domain.
My idea is to work on 'Low Power Multiplier' to minimize it's power , delay and increase the speed of multiplier.
I don't know whether the multiplier domain is saturated or not . Is there any good area other than multiplier in Low Power VLSI ?

 

[Fish4Fun]

gstekboy, Welcome to the forum! Guess no one else is going to bite, so....

VLSI ("Very Large Scale Integration") is a somewhat qualitative descriptor....in historical context it could mean anything from a 74xx Logic chip to Intel's bleeding edge multi-core processor family....Likewise, "low power", again is a qualitative descriptor that implies a comparison to similar existing devices....So, I have to ask, what do you mean by "I selected 'Low Power VLSI...'"? Are you "working on" substrate processes and attempting to reduce feature size to reduce power in a new VLSI family, or do you mean you want to select a commercially available low power VLSI device and attempt to reduce power consumption via implementation of firmware/hardware?

If the venue is the substrate level then you should have a well-formed plan or at the very least a theory in mind or provided to you...so, I will assume the project is to select an existing commercially available chip and attempt to optimize some function with respect to power consumption....With this in-mind, I would suggest you explore one of the FPGA development boards. FPGAs are frequently used to prototype processor cores and complex ASIC logic functions...they are available in a wide range of speed/size/power levels and are virtually infinitely configurable, though if you are unfamiliar with HDLs (Hardware Definition Languages) in general then you may be biting off a lot for an undergraduate course.

On the list of "projects" other than a "multiplier", you might consider any of a number of digital signal processing tasks, encryption/decryption implementations, or perhaps even Graphics memory mapping....the list of systems and subsystems that might benefit from lower power consumption is quite long, but addressing power consumption via software/firmware optimization is more likely a doctoral thesis than an undergraduate project. Likewise firmware//software optimization of "multiplier routines" or other routines to reduce power consumption is generally platform specific and might be difficult to demonstrate. There are published documents describing "differential power analysis" as a potential vulnerability in otherwise secure encryption/decryption routines, specifically with respect to "smart cards". Differential power analysis attempts to glean information about the keys used in encryption/decryption by carefully studying the "power signature" of particular opcodes. The general idea is that the power signature of any particular opcode in any given micro-controller differs slightly based on the relative number of "1s" in the operands, result and the number of SREG flags set/cleared as a result of the execution of the opcode. I am NOT suggesting an investigation into differential power analysis, but merely pointing out that there is documentation verifying that power consumption is, to some small degree, dependent not only on the optimization level of the firmware/software, but also on the data which it is processing...

For an undergraduate level course it might be interesting to investigate the affects of data on power consumption. For instance, you might select a micro-controller and write a simple loop that repeatedly uses a single opcode to perform an operation (obviously there will be more than one opcode involved, but as long as there is only one opcode that manipulates data, and the remaining opcodes are the same, any resulting power difference would seem to indicate proof-of-concept). There are a few different approaches you might consider: 1) Log the power consumption of the system over a fairly large time period in an attempt to identify a difference in "average" power consumption...but this might prove difficult to implement. 2) Using a high quality capacitor (perhaps a "super capacitor" 1F ?) as your power source, measure the number of iterations between two specific voltage levels using a pair of differential op amps with stable voltage references at....say 5.00V and 4.90V to "start" & "start" the count. Obviously the results here will depend on accuracy//stability of your voltage detection circuits....you will also want to ensure that the sensing impedances are high enough not to impact the test circuit 3) If you have access to a lab-grade DSO you can observe the power signatures directly and then calculate the cumulative effects.

Example Code:

AVR ASM Code Sample for #1 & 3:
.equ  Dat = $FF   ;To contrast "$FF", replace with $00, for other "tests" try ($55, $AA) &  ($F0, $0F)
Loop:             ;<<==Begin Test
ldi  r16, Dat     ;
                  ;	     
add  r16, r16     ;<<==Target opcode
jmp  Loop         ;

AVR ASM Code Sample for #2:
.equ  Dat = $FF   ;To contrast "$FF", replace with $00, for other "tests" try ($55, $AA) &  ($F0, $0F)
.equ  IoPin = 0   ;Assuming Device has ProtD, Set to any PortD Pin you like
sbi   DDRD, IoPin ;Set PORTD.IoPin as Output
Loop:             ;<<==Begin Test
     ldi  r16, Dat     ;In different Tests replace "$FF" with $00, for other "tests" try $55, $AA, $F0, $0F	     
     add  r16, r16     ;<<==Target opcode
     cbi  PortD, IoPin ;Clear PortD Pins
     ldi  r16, Dat     ;The same Operation is performed a second time 
     add  r16, r16     ;
     sbi  PortD, IoPin ;
     jmp  loop         ;

Good Luck!

Fish