Summary of the difference between FPGA and ASIC.

In this article, we will provide you the differences between FPGA and ASIC.

There are many differences between FPGA and ASIC. The logic of ASIC is usually much larger than that of FPGA. There is an order of magnitude difference in gate numbers, and the running clock is much higher than FPGA. Moreover, FPGA is relatively flexible than ASIC because it can be programmed, but only in terms of RTL design:

(1) ASIC tends to be more conservative, any changes to logic needed careful consideration, and make alternative choices in case of a correction. Any modification to RTL is almost incremental, and even if the previous logic is wrong, it will not be deleted, but one more branch is made.

(2) ASIC has higher requirements for coding style. Coding style requirements for all modules are consistent, thus favoring the fault check.

(3) ASIC design pays more attention to the clock and reset. In particular, clocks are critical to the design of ASIC, and reset is critical to BIST testing. ASIC uses libraries to design in this respect. ASIC usually does not use a counter to divide frequencies, which can lead to unclean clocks. Unless it's a very low-frequency clock, ASIC is also much more cautious about signal processing across clock domains. The closing and opening of the clock also need to be strictly checked.

(4) ASIC has to consider the problems of SCAN testing and BIST, so it is necessary to do BIST insertion for SRAM when designing and to reserve interfaces for SCAN. Although most of the interfaces are done by tools, RTL authors often have to do some top-level complex work manually, logic such as the source of the SCAN clock.

(5) FPGA often uses existing IP, it needs to consider the balance of resources because there is a problem of resource waste in FPGA. ASIC rarely needed to consider this problem, the main consideration of it is its performance and power consumption, except SRAM and CLK which is related to reset in logic choice, the other are handwritten. So the logic is basically no waste, and more compact.

(6) ASIC timing is more predictable and adjustable, so it can write a lot of logic.

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Ivory Grand

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