6-layer PCB stack up

[Mr.CRC]

I rarely have a slot cut out of a plane. What I commonly have is a
plane that has a bunch of power pours, pretty much paving the plane
with patches separated by small gaps. That might be the "reference
plane" to a surface microstrip, or we might have an embedded stripline
between a solid ground plane and a multi-pour power plane.

If you treat the power plane like a solid sheet of copper, it works.
The discontinuity that you typically get is comparable to the
impedance variation you see from the fiberglass weave.

I don't know why people make such a big deal about reference planes
and return currents and bypassing. On a multilayer board, most
anything reasonable works. For fairly fast stuff, like FPGA clocks,
impedance and crosstalk control does matter. I could teach someone
most of what they need to know about this in 45 minutes.

That's not as impressive to my boss as "getting this stuff right
requires a lifetime of study of this big stack of (Howard Johnson, heh
heh) books!"

 

[Mr.CRC]

Of course not. But you've got the dimensions wrong: the gap might be
0.25mm (i.e., 10 mil, or even less), not 1mm. This lets out a lot less
flux already (both E and M).

Be interesting to see just how much crap gets lost over such a
discontinuity; like a scope probe with ground clip, it's not going to be
pretty by any stretch, but it's also not going to be as bad as DC
intuition suggests.

This would only be true of a board with a single, slotted ground plane,
which is silly by any measure. The correct analogy would be if you took
that injured coax cable and wrapped it with copper foil tape, so that
the shield is supported all around by a secondary ground plane.

Yes, this is a better analogy, and what I had in mind just a few moments
ago whilst thinking about this at breakfast.

The
current flows as displacement current in the outer jacket; high
frequencies will hardly know the difference.

Very high frequencies will know the difference, on the order of slot
width ~= 1/20th wavelength. Low frequencies will know as well, but
that's easy, because at low frequencies you can simply hook a wire to
either side of the gap and handle the LF current that way.

John uses many planes, and only two planes are required for operation --
a slot in one pour, or a gap between different pours, supported beneath
by pours bridging said gap.

Interesting stuff. Thanks for the input.

 

[Mr.CRC]

I rarely have a slot cut out of a plane. What I commonly have is a
plane that has a bunch of power pours, pretty much paving the plane
with patches separated by small gaps. That might be the "reference
plane" to a surface microstrip, or we might have an embedded stripline
between a solid ground plane and a multi-pour power plane.

If you treat the power plane like a solid sheet of copper, it works.
The discontinuity that you typically get is comparable to the
impedance variation you see from the fiberglass weave.

I don't know why people make such a big deal about reference planes
and return currents and bypassing. On a multilayer board, most
anything reasonable works. For fairly fast stuff, like FPGA clocks,
impedance and crosstalk control does matter. I could teach someone
most of what they need to know about this in 45 minutes.

So if you had this stack (not saying this would be done in a real PCB):

1. signal trace
2. power layer with multiple tiles of power, all separated by gaps
3. solid ground plane

that the impedance of traces in layer one would be computable based on
the distance to layer 2, and that the gaps wouldn't matter because layer
3 carries the HF current over the gaps?


What about a situation like this, typical of the 4-layer boards I get
from Advanced Circuits, if I don't ask for anything non-standard:


layer 1
0.010in prepreg
layer 2
0.040in core
layer 3
0.010in prepreg
layer 4

In this case the inner layers are quite far apart. So for whatever
inner layer is GND, the signal on the far side will be 0.010in from the
power plane with cuts, and 0.050in from the continuous ground plane.

Does this start to become a problem?


Hopefully some day I'll have time to make some experiment boards (fat
chance).

 

[Tim Williams]

One thing that bugs me about your post is that you spend a lot of time
talking about "capacitance." Nobody cares about capacitance. The
only important quantities are the reactances, and those vary with
frequency.

When a person speaks of "capacitance" at high frequencies, what is really
meant is "the impedance of the structure is less (usually significantly
less) than the impedance of the related signal lines".

A trace's characteristic impedance might be 50 or 110 ohms or whatever on
L1, relative to the ground plane on L2, but the impedance from any geometry
in L2 (disparate pours, or a slot in a single pour, etc.) relative to the
(solid or overlapping) ground plane on L3 beneath it results in a
vanishingly small impedance (< 10 ohms) between those pours/planes for
"most" higher frequencies.

For lower frequencies (where the induced wave has had a chance to bounce
around the bounds of the pour a few times), the inductance of vias, traces
and packages comes into play and bypass caps take over. As a result, the
impedance of the pour may vary quite a bit with frequency, and you may get
unlucky with particular combinations of pour shapes, and where the bypass
caps are placed on them (i.e., avoid harmonically related spacings to
prevent bypasses enhancing nodes at some resonant frequency), but for the
most part, with random placement, you'll have good luck that any resonances
that occur will still be low impdance.

Note that a trace crossing a slot in a single pour is identical to it
crossing separate pours, as long as the frequency is higher than the quarter
wave length to the nearest corner of the slot -- until the energy reaches
the end of the slot, it doesn't "know" that it actually IS a slot, or just
another gap.

Terms like "not much" don't help when your interplane C turns out to
be more effective at coupling than at bypassing. And if slot antennas
don't terrify you, you're either really good at your job, really bad
at it, or working on something uninteresting.

A slot antenna, roughly speaking, looks like an inductance (defined by the
flux that goes through the enclosed slot area) parallel with a capacitance
(the capacitance of the sides of the slot to each other, roughly), limited
by the Q of copper and radiation resistance. If L is small and C is large
(which are both true when a slot is underlaid by a contiguous ground plane),
then even for very high Q (which is unlikely, because the inductive Q will
be poor with so much shielding), the impedance of the resonant tank thus
formed can still be very small. Though the resonance will be detectable, it
need not be significant in relation to digital signals (e.g., <20 ohms
versus a ~100 ohm trace crossing it), or in regards to EMC (harder to define
a quantity, admittedly may be more stringent than mere signal quality
requires).

In short, if you make a really bad antenna, it should come as no surprise
that it doesn't necessarily radiate much of significance, nor will it
likewise have any significant effect on circuit operation. It will still be
there, and be detectable through suitable means, but principles aren't as
important as real result.

The dynamics will be there, but even without significant damping, it needn't
necessarily be an automatic failure. This is important to remember: I'm
pretty sure this is one error Tesla himself made -- resonant circuits simply
do not charge up continuously for all time; all real tanks contain a
dissipative element, which acts to suppress the resonance and spread it out.

Tim

 

[josephkk]

It's hard to enforce direction discipline on layer 1. All the
surface-mount parts shoot signals in all directions.

Um. Vias to other layers adjacent to or inside the pad is not
impermissible. It depends a lot on how many pads need controlled
impedances and why.

?-/