crazyfordigits
- Oct 12, 2014
- 1
- Joined
- Oct 12, 2014
- Messages
- 1
Hi Everybody,
I am currently trying to implement a carry save adder tree (like a Wallace tree) in verilog but I am really confused about the addition arithmetic of carry save adder trees (I understand how a single carry save adder works). I was looking at an example on p.33 of this ducument http://www.ee.ic.ac.uk/hp/staff/dmb/courses/dig2/5_Adder.pdf and I don't understand point 3 of the notes, why can we just use 4 bit CSAs even though the sum clearly will go into 5 and 6 bits? I think the example given on the page just happened to have its least significant bits to be zero so we can use 4 bit CSA for everything, but in general I think we should use 6 bit CSAs for the entire circuit?
Also, I spent the entire day yesterday trying to find a Wallace adder tree implementation example, if anyone has a good reference I'll really appreciate your help. Thank you! Also, I'm new to this forum so please be kind to me. I am open to constructive feedback/criticism. Thanks again!
I am currently trying to implement a carry save adder tree (like a Wallace tree) in verilog but I am really confused about the addition arithmetic of carry save adder trees (I understand how a single carry save adder works). I was looking at an example on p.33 of this ducument http://www.ee.ic.ac.uk/hp/staff/dmb/courses/dig2/5_Adder.pdf and I don't understand point 3 of the notes, why can we just use 4 bit CSAs even though the sum clearly will go into 5 and 6 bits? I think the example given on the page just happened to have its least significant bits to be zero so we can use 4 bit CSA for everything, but in general I think we should use 6 bit CSAs for the entire circuit?
Also, I spent the entire day yesterday trying to find a Wallace adder tree implementation example, if anyone has a good reference I'll really appreciate your help. Thank you! Also, I'm new to this forum so please be kind to me. I am open to constructive feedback/criticism. Thanks again!
