Jim said:
Mike, is that an LTspice-specific model or is it a subcircuit?
The VDMOS model* with built-in nonlinear Cdg is LTspice specific.
Does it solve Win's low-current fretting issues?
As Mike stated above, the VDMOS model does not. (Like most of the
rest of the models, current falls off the face of the earth in the
sub threshold region.) Apparently level=7 models address the sub
threshold region, but didn't Win report that he thought the bend of
the curve wasn't quite right? (never checked myself)
The problem with all MOSFET models is that, as far as I know, none
address the dependence of terminal capacitances (and their loss
elements) on multiple terminal voltages (i.e. Cdg=f(Vdg,Vgs), etc.).
This effect is most clear when gate voltage is driven negative. It
seems that as the terminal boundaries move around within the device,
significant capacitance is "switched" from between one set of
terminals to another.
Unfortunately, there isn't a lot in the literature about straight-
forward models for this, at least that I've found (good references
always welcome).
[*} From the LTspice Help File:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The discrete vertical double diffused MOSFET transistor(VDMOS) popu-
larly used in board level switchmode power supplies has behavior that
is qualitatively different than the above monolithic MOSFET models.
In particular, (i) the body diode of a VDMOS transistor is connected
differently to the external terminals than the substrate diode of a
monolithic MOSFET and (ii) the gate-drain capacitance(Cgd) non-linear-
ity cannot be modeled with the simple graded capacitances of monolithic
MOSFET models. In a VDMOS transistor, Cgd abruptly changes about zero
gate-drain voltage(Vgd). When Vgd is negative, Cgd is physically based
a capacitor with the gate as one electrode and the drain on the back of
the die as the other electrode. This capacitance is fairly low due to
the thickness of the non-conducting die. But when Vgd is positive, the
die is conducting and Cgd is physically based on a capacitor with the
thickness of the gate oxide.
Traditionally, elaborate subcircuits have been used to duplicate the
behavior of a power MOSFET. A new intrinsic spice device was written
that encapsulates this behavior in the interest of compute speed, reli-
ability of convergence, and simplicity of writing models. The DC model
is the same as a level 1 monolithic MOSFET except that the length and
width default to one so that transconductance can be directly specified
without scaling. The AC model is as follows. The gate-source capaci-
tance is taken as constant. This was empirically found to be a good
approximation for power MOSFETS if the gate-source voltage is not driven
negative. The gate-drain capacitance follows the following empirically
found form:
Negative Vgd: Ggd = C*atan(a*Vgd)+D
Positive Vgd: Gdg = A*tanh(a*Vgd)+B
For positive Vgd, Cgd varies as the hyperbolic tangent of Vgd. For neg-
ative Vdg, Cgd varies as the arc tangent of Vgd. The model parameters a,
Cgdmax, and Cgdmax parameterize the gate drain capacitance. The source-
drain capacitance is supplied by the graded capacitance of a body diode
connected across the source drain electrodes, outside of the source and
drain resistances.
name parameter units default example
------------------------------------------------------
l Length m 1. 2.
w Width m 1. 1.
Rg Gate ohmic resistance Ohms 0.
Rds Drain-Source shunt Ohms 0.
resistance
VTO zero-bias threshold V 0. 1.
voltage
KP transconductance A/V 1. 3.
PHI surface potential V 0.6 0.65
LAMBDA channel-length 1/V 0. 0.02
modulation
Cbd zero-bias B-D F 0. 20f
junction capacitance
Cbs zero-bias B-S F 0. 20f
junction capacitance
Rd Drain ohmic resistance Ohms 0.
Rs Source ohmic resistance Ohms 0.
Cgs Gate-source overlap F 0. 4e-11
capacitance
Cgdmin Minimum non-linear G-D F 0. 4e-11
capacitance
Cgdmax Maximum non-linear G-D F 0. 4e-11
capacitance
a non-linear Cgd 1 1. .5
capacitance parameter
Is Body diode saturation A 1e-14 1e-15
current
Rb Body diode ohmic Ohms 0.
resistance
n Body diode emission - 1.
coefficient
Cjo Body diode junction F 0. 4e-11
capacitance
Vj Body diode junction V 0.75
potential
m Body diode grading - 0.5 0.5
coefficient
Fc Body diode forward - 0.5
bias junction fit
parameter
tt Body diode transit time sec 0. 0.1n
Eg Body diode activation eV 1.11
energy for temperature
effect on Is
Xti Body diode saturation - 3
current temperature
exponent
nchan[*] N-channel VDMOS - (true)
pchan[*] P-channel VDMOS - (false)
Tnom Parameter measurement °C 27
temperature
Kf Flicker noise coefficient - 0
Af Flicker noise exponent - 0
*]The model name VDMOS is used both for a N-channel and P-channel device.
The polarity defaults to N-channel. To specify P-channel, flag the model
with the keyword "pchan", e.g., ".model xyz VDMOS(Kp = 3 pchan)" defines
a P-channel transistor.
