Idea for Smart Charge Amplifier

[Robert Scott]

While developing a signal conditioner for a piezo force sensor, I came
up with a method that looks intriguing. Basically a charge amplifier
accumulates charge on a capacitor which is buffered by a very
high-impedance amplifier. The traditional method of dealing with the
AC nature of the circuit is to place a very high resistance around the
capacitor. This leads to a sometimes difficult tradeoff between
sensitivity and low frequency response. A large capacitor gives
better low-frequency response, but it also lowers the sensitivity
(volts per Coulomb ). Ultimately some reference needs to be made to
the application. In the case of a force sensor, if absolute force is
needed, then there must be a provision for doing a tare shortly before
beginning the measurement, which must last only as long as the leakage
resistances allow.

My idea is to replace the bleed resistor with intelligent control. If
a microcontroller is involved anyway, then it can know when a tare is
possible. At that time, it can inject a controlled amount of charge
into the capacitor through an ultra low leakage diode. By reading the
output of the charge amplifier, the micro can form a closed loop to
force a known charge into the capacitor and thus perform a tare.

Currently, my design charges a capacitor from the piezo sensor, which
is then buffered by a source-follower JFET stage (with less than 20 pA
gate leakage). The micro reads the source voltage. There is no
resistor around the capacitor, other than the inherent leakage of the
circuit components. This optimizes the low-frequency response without
the use of exotic multi-gigohm resistors. Using the gate-source
junction of the same type of FET as low-leakage diodes, the micro
injects (+) or (-) charge during the tare period. What do you think
of this approach?


-Robert Scott
Ypsilanti, Michigan

 

[Phil Hobbs]

While developing a signal conditioner for a piezo force sensor, I came
up with a method that looks intriguing. Basically a charge amplifier
accumulates charge on a capacitor which is buffered by a very
high-impedance amplifier. The traditional method of dealing with the
AC nature of the circuit is to place a very high resistance around the
capacitor. This leads to a sometimes difficult tradeoff between
sensitivity and low frequency response. A large capacitor gives
better low-frequency response, but it also lowers the sensitivity
(volts per Coulomb ). Ultimately some reference needs to be made to
the application. In the case of a force sensor, if absolute force is
needed, then there must be a provision for doing a tare shortly before
beginning the measurement, which must last only as long as the leakage
resistances allow.

My idea is to replace the bleed resistor with intelligent control. If
a microcontroller is involved anyway, then it can know when a tare is
possible. At that time, it can inject a controlled amount of charge
into the capacitor through an ultra low leakage diode. By reading the
output of the charge amplifier, the micro can form a closed loop to
force a known charge into the capacitor and thus perform a tare.

Currently, my design charges a capacitor from the piezo sensor, which
is then buffered by a source-follower JFET stage (with less than 20 pA
gate leakage). The micro reads the source voltage. There is no
resistor around the capacitor, other than the inherent leakage of the
circuit components. This optimizes the low-frequency response without
the use of exotic multi-gigohm resistors. Using the gate-source
junction of the same type of FET as low-leakage diodes, the micro
injects (+) or (-) charge during the tare period. What do you think
of this approach?

This isn't especially new. It can work better than resistor reset if
you use correlated double sampling--i.e. reset, digitize, integrate,
digitize, reset.....

Otherwise, the noise is just the same--kT/C rms.

Cheers,

Phil Hobbs

 

[Phil Hobbs]

My idea is to replace the bleed resistor with intelligent control. If
a microcontroller is involved anyway, then it can know when a tare is
possible. At that time, it can inject a controlled amount of charge
into the capacitor through an ultra low leakage diode. By reading the
output of the charge amplifier, the micro can form a closed loop to
force a known charge into the capacitor and thus perform a tare.

Currently, my design charges a capacitor from the piezo sensor, which
is then buffered by a source-follower JFET stage (with less than 20 pA
gate leakage). The micro reads the source voltage. There is no
resistor around the capacitor, other than the inherent leakage of the
circuit components. This optimizes the low-frequency response without
the use of exotic multi-gigohm resistors. Using the gate-source
junction of the same type of FET as low-leakage diodes, the micro
injects (+) or (-) charge during the tare period. What do you think
of this approach?

This isn't especially new. It can work better than resistor reset if
you use correlated double sampling--i.e. reset, digitize, integrate,
digitize, reset.....

Otherwise, the noise is just the same--kT/C rms. No matter what sort of
switch you use, you always get that uncertainty as a minimum.

Cheers,

Phil Hobbs

 

[Phil Hobbs]

My idea is to replace the bleed resistor with intelligent control. If
a microcontroller is involved anyway, then it can know when a tare is
possible. At that time, it can inject a controlled amount of charge
into the capacitor through an ultra low leakage diode. By reading the
output of the charge amplifier, the micro can form a closed loop to
force a known charge into the capacitor and thus perform a tare.

Currently, my design charges a capacitor from the piezo sensor, which
is then buffered by a source-follower JFET stage (with less than 20 pA
gate leakage). The micro reads the source voltage. There is no
resistor around the capacitor, other than the inherent leakage of the
circuit components. This optimizes the low-frequency response without
the use of exotic multi-gigohm resistors. Using the gate-source
junction of the same type of FET as low-leakage diodes, the micro
injects (+) or (-) charge during the tare period. What do you think
of this approach?

This isn't especially new. It can work better than resistor reset if
you use correlated double sampling--i.e. reset, digitize, integrate,
digitize, reset.....

Otherwise, the noise is just the same--kT/C rms. No matter what sort of
switch you use, you always get that uncertainty as a minimum.

Cheers,

Phil Hobbs

 

[Phil Hobbs]

My idea is to replace the bleed resistor with intelligent control. If
a microcontroller is involved anyway, then it can know when a tare is
possible. At that time, it can inject a controlled amount of charge
into the capacitor through an ultra low leakage diode. By reading the
output of the charge amplifier, the micro can form a closed loop to
force a known charge into the capacitor and thus perform a tare.

Currently, my design charges a capacitor from the piezo sensor, which
is then buffered by a source-follower JFET stage (with less than 20 pA
gate leakage). The micro reads the source voltage. There is no
resistor around the capacitor, other than the inherent leakage of the
circuit components. This optimizes the low-frequency response without
the use of exotic multi-gigohm resistors. Using the gate-source
junction of the same type of FET as low-leakage diodes, the micro
injects (+) or (-) charge during the tare period. What do you think
of this approach?

This isn't especially new. It can work better than resistor reset if
you use correlated double sampling--i.e. reset, digitize, integrate,
digitize, reset.....

Otherwise, the noise is just the same--kT/C rms. No matter what sort of
switch you use, you always get that uncertainty as a minimum.

Cheers,

Phil Hobbs

 

[Winfield Hill]

Phil Hobbs wrote...

This isn't especially new. It can work better than resistor
reset if you use correlated double sampling--i.e. reset,
digitize, integrate, digitize, reset.....

Otherwise, the noise is just the same--kT/C rms. No matter
what sort of switch you use, you always get that uncertainty
as a minimum.

Right, it's hard to be new on the fourth retelling.

 

[Phil Hobbs]

Phil Hobbs wrote...



Right, it's hard to be new on the fourth retelling.

Yeah, well, my silly IP tunnelling work net connection s-s-s-stutters,
w-w-what can I t-tell you.

Cheers,

Phil Hobbs

 

[Robert Scott]

This isn't especially new. It can work better than resistor reset if
you use correlated double sampling--i.e. reset, digitize, integrate,
digitize, reset.....

Otherwise, the noise is just the same--kT/C rms. No matter what sort of
switch you use, you always get that uncertainty as a minimum.

Could you please explain correlated double sampling? Does it mean
this:

1. Reset by forcing a tare charge onto the capacitor
2. Read the amplifier output to deterimine the error in step 1
3. Integrate charge
4. Read amplifier output and compare it with the digital zero read in
step 2.


-Robert Scott
Ypsilanti, Michigan

 

[Phil Hobbs]

Could you please explain correlated double sampling? Does it mean
this:

1. Reset by forcing a tare charge onto the capacitor
2. Read the amplifier output to deterimine the error in step 1
3. Integrate charge
4. Read amplifier output and compare it with the digital zero read in
step 2.


-Robert Scott
Ypsilanti, Michigan

Right--reset, digitize, integrate, digitize, reset, digitize, integrate,
digitize, reset, digitize.....

CCDs have exactly the same problem, and this is how CCD readouts are designed.

Cheers,

Phil Hobbs