Passing of logics from nmos and pmos

[Udit gupta]

Hi!
It is quite known that nmos passes logic 0 as it is and logic 1 with some distortion(Vdd - Vtn), vice-versa for pmos.

Could anybody help me with the detailed approach to getting to this conclusion .
(I think it has something to do with the MOS going to linear and saturation region)

Thanks

 

[(*steve*)]

Ask yourself how a logic 0 and a logic 1 are produced by the output of such logic. If it's not clear, compare it to CMOS.

What (in relative terms) is the output current sinking and sourcing capability? How would this affect the signal if there was any stray capacitance?