On 2005-09-13 said:
I think you're absolutely correct. I had been wondering why on the dev
board they used an 18.432Mhz crystal. So am I understanding your post
correctly in that the master clock has to be 48Mhz for USB to be
functional? Would it be possible to normally run at 55Mhz and then when
a connection is detected on the USB connector have it switch down to
48? Thanks,
Caveat lector -- I'm basing all my answers on my reading of the
preliminary datasheet. I haven't managed to get my hands on a part
yet, so everything I say could be wrong.
The short answer is yes, I think so.
This chip has lots of clocks, and it took me some time to sort it all
out, so I might as well share what I learned. The fundamental clock
sources are the internal RC oscillator (SLCK or "slow clock",
nominally 32.768kHz, but not very precise or stable), and the main
clock, driven by either a crystal oscillator or an external clock
source. Note that this is called the "main" clock (MAINCK), which is
different from the "master" clock, but before we get to that there's
also the PLL clock (PLLCK), which is driven by the main clock and
includes a programmable divider and multiplier. This results in three
primary clocks available in the system - slow clock, main clock, and
PLL clock.
The master clock (MCK), which you mention, can be based on any one of
these three clocks, and further more it has a power-of-2 prescaler
which can divide the clock so that the MCK is slower than its source
if you like. The MCK is the source for the processor clock (PCK) and
all the peripheral clocks, except for the real time timer (which,
regrettably, must use the slow clock, and therefore can't be relied
upon for long-term stability), the other timer/counters (which have
many possible clock sources, but that's irrelevant to our current
discussion), and, finally getting to your question, the USB clock
(USBCK). The USB clock can be driven only be the PLL clock, though
there is a divider which can divide PLLCK by 1, 2, or 4. So, if you
want to use USB, PLLCK must be 48MHz, 96MHz, or 196MHz, +/-0.25%.
So what's the net effect of this, if you want to use USB? USBCK must
be driven by PLLCK, which must be driven by MAINCK, which can be
driven by either crystal oscillator or external clock source. MAINCK,
therefore, must be chosen such that the divider/multiplier in the PLL
can scale it to a precise multiple of 48MHz, and 18.432MHz happens to
be a good choice for this (*125 /48). This, unfortunately, limits
your master clock, which drives the processor, to either the slow
clock (probably not what you want), or something based on 18.432MHz.
You can get very close to 55MHz from 18.432MHz by using the PLL (*185
/62, for example), but you can't use the PLL for this at the same time
you're using it to drive USBCK at 48MHz. So, while you're using USB,
you have to run the master clock at either 48MHz, 18.432MHz (straight
from MAINCK), or 32.768kHz (SLCK).
But, you absolutely can reprogram all the clock sources on the fly, so
long as you follow the procedures documented in the datasheet, so that
you normally run at close to 55MHz but reprogram the PLL and drop down
to 48MHz when you need USB. Note that you'll have to have the USB
peripheral completely disabled while at 55MHz, so you'll need another
way to detect USB (sensing voltage on the USB +5V pin, for example).
Hope that helps, and please correct me if you find that I'm wrong
about any of this!
