xilinx virtex2 ISP using hc12

[blisca]

Hello
i started last year to work(play?) with a 16bit 9s12 microcontroller,having
some surplus scraped xc2v2000 fpga's and a little experience in vhdl i
would like to use these fpga but i need some external memory for storing
permanently the configuration data.
Due to impossibility of realizing a PCB to mount a flash and the lot of
connections,i think if it is possible to use the 9s12 to program the fpga.I
would like to use it because having a good programmer with in -circuit
debugger i could check if the system is working in correct manner during
development phase.
Any ideas?
Thank you.

Diego
Milano
Italy

 

[John Larkin]

Hello
i started last year to work(play?) with a 16bit 9s12 microcontroller,having
some surplus scraped xc2v2000 fpga's and a little experience in vhdl i
would like to use these fpga but i need some external memory for storing
permanently the configuration data.
Due to impossibility of realizing a PCB to mount a flash and the lot of
connections,i think if it is possible to use the 9s12 to program the fpga.I
would like to use it because having a good programmer with in -circuit
debugger i could check if the system is working in correct manner during
development phase.
Any ideas?
Thank you.

Diego
Milano
Italy

Sure. We always program our FPGAs from a uP, since all of our products
have a uP anyhow.

You'll need some way to merge the Xilinx bitstream data into your uP
program image, then you'll need to write a simple routine to reset the
fpga, un-reset it (PROGB pin), and then bit-bang the config data into
it, slave serial mode, using CCLK and DIN pins. It's fairly simple.

I have a PowerBasic program that builds a uP rom inage from an S28
program file and a .RBT config file, and a bit-banger in 68K assembly,
available as examples if nothing else.

Be sure to terminate CCLK at the fpga, as they are very sensitive to
ringing, and bit-bang an extra 32 bits of anything, for luck.

John

 

[PeteS]

Sure. We always program our FPGAs from a uP, since all of our products
have a uP anyhow.

You'll need some way to merge the Xilinx bitstream data into your uP
program image, then you'll need to write a simple routine to reset the
fpga, un-reset it (PROGB pin), and then bit-bang the config data into
it, slave serial mode, using CCLK and DIN pins. It's fairly simple.

I have a PowerBasic program that builds a uP rom inage from an S28
program file and a .RBT config file, and a bit-banger in 68K assembly,
available as examples if nothing else.

Be sure to terminate CCLK at the fpga, as they are very sensitive to
ringing, and bit-bang an extra 32 bits of anything, for luck.

John

See XAPP800 (registration required) at Xilinx. This uses a CoolRunner
to bitbang a FPGA using a SPI flash for storage, but the bit bang VHDL
is straightforward and could easily be ported to your architecture and
language of choice.

Cheers

PeteS

 

[blisca]

thank you to you both for the good support and hints!