fast switching circuit/spice sim

[steve]

Hi,

I'm trying to create a high speed enable/disable control for an
analogue signal. I found some SD5400 DMOS ICs (quad DMOS N-type FETs)
from Linear Systems that switch quickly (2ns) and I've got a simple
spice circuit to test this.

The test circuit is: a 2V p-p (with 1V DC offset) sinewave applied to
the drain, a DC control voltage applied to the gate, and a 1MOhm load
(modelling the input impedance of a buffer) at the source, ie:

Vsin in GND SIN(1 1 1000k 0 0)
M1 in gate out GND sd5400cy
Vdc gate GND DC 1
R1 out GND 1000k

However, the circuit doesn't simulate as expected. With a Vg = 1V, the
FET is off and the output is pulled to ground via the load resistance.
This is as expected.

But when I apply a 5V gate voltage (so that the gate-source voltage is
always greater than the Vth=1.2V of the FET), it turns on but the
output looks distorted, as shown here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-5V.pdf

Shouldn't the output be following the input? The FET is operating as a
SPST switch, and its Rds(on) is insignificant in comparison to the
load.

Also, I've found that increasing Vg decreases the deviation of the
output from the input, ie with Vg=15V and Vg=100V:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-15V.pdf
http://www.teamlinux.org.uk/steve/spice/switch_Vg-100V.pdf

For completeness, Vg=1V is also included:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-1V.pdf

Can anyone give me any hints as to what is going on here?

Is there something wrong with my idea of using a FET as a switch
directly? Am I missing anything?

Cheers,

Steve

 

[Jim Thompson]

Hi,

I'm trying to create a high speed enable/disable control for an
analogue signal. I found some SD5400 DMOS ICs (quad DMOS N-type FETs)
from Linear Systems that switch quickly (2ns) and I've got a simple
spice circuit to test this.

The test circuit is: a 2V p-p (with 1V DC offset) sinewave applied to
the drain, a DC control voltage applied to the gate, and a 1MOhm load
(modelling the input impedance of a buffer) at the source, ie:

Vsin in GND SIN(1 1 1000k 0 0)
M1 in gate out GND sd5400cy
Vdc gate GND DC 1
R1 out GND 1000k

However, the circuit doesn't simulate as expected. With a Vg = 1V, the
FET is off and the output is pulled to ground via the load resistance.
This is as expected.

But when I apply a 5V gate voltage (so that the gate-source voltage is
always greater than the Vth=1.2V of the FET), it turns on but the
output looks distorted, as shown here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-5V.pdf

Shouldn't the output be following the input? The FET is operating as a
SPST switch, and its Rds(on) is insignificant in comparison to the
load.

Also, I've found that increasing Vg decreases the deviation of the
output from the input, ie with Vg=15V and Vg=100V:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-15V.pdf
http://www.teamlinux.org.uk/steve/spice/switch_Vg-100V.pdf

For completeness, Vg=1V is also included:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-1V.pdf

Can anyone give me any hints as to what is going on here?

Is there something wrong with my idea of using a FET as a switch
directly? Am I missing anything?

Cheers,

Steve

Looks like your device needs at least 10V VGS to be "ON"... note _VGS_

...Jim Thompson

 

[steve]

Hi Jim,

The datasheet specifys Vgs(th)(max) as 1.5V - are you saying that the
transition region of the device from being off to being on stretches
from 1.5V to 10V? Or have I misunderstood the datasheet, and does
Vth=10V, not 1.5V?

Cheers,

Steve

 

[Jim Thompson]

Hi Jim,

The datasheet specifys Vgs(th)(max) as 1.5V - are you saying that the
transition region of the device from being off to being on stretches
from 1.5V to 10V? Or have I misunderstood the datasheet, and does
Vth=10V, not 1.5V?

Cheers,

Steve

Threshold (Vgs(th) or simply Vth) means just that, THRESHOLD where
current just begins, series R drops as Vgs increases.

Win can provide more detail... he's the expert around here on discrete
MOSFET's (I design chips... I very rarely get flux on my fingers

...Jim Thompson

 

[Joerg]

Hello Jim,

Looks like your device needs at least 10V VGS to be "ON"... note _VGS_

They are usually happy with 5V Vgs and actually spec'd for it if you can
take 75 ohms. For under 50 ohms it needs to be 10V. But yes, it has to
be Vgs so the gate voltage need to be in addition of whatever the source
is riding at.

Steve: Don't forget to connect the substrate when you try it out. It's
separate on these.

Regards, Joerg

 

[John Perry]

Hi Jim,

The datasheet specifys Vgs(th)(max) as 1.5V - are you saying that the
transition region of the device from being off to being on stretches
from 1.5V to 10V? Or have I misunderstood the datasheet, and does
Vth=10V, not 1.5V?

Steve, you need to look at page 2 of the datasheet, in the rows labelled
"Drain-Source On-Resistance" There you'll see the details of Joerg's
description. Now, if your gate voltage is high enough above the highest
signal voltage, the fet remains low-resistance.

In your 5v gate plot, however, the peaks of the signal cause the source
voltage to approach the gate voltage so that the fet resistance rises
high enough to change the signal going to your output. You don't say
what your circuit is, but your output waveform is about right for this
effect.

How did you manage to get the fets to survive a 100V gate voltage? They
should all have fried instantly (p. 2, absolute maximum says +30, -25).
Are all your fets shorted now? You should check drain-source
resistance with Vgs = 0. They're probably dead.

John Perry

 

[steve]

Hello Jim,


They are usually happy with 5V Vgs and actually spec'd for it if you can
take 75 ohms. For under 50 ohms it needs to be 10V. But yes, it has to
be Vgs so the gate voltage need to be in addition of whatever the source
is riding at.

I've re-run the simulations to see whether this is the case. First, I
tried with Vg=7V, so that Vgs never drops below 5V. The results are
here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-7V.pdf

The output looks a lot better than with Vg=5V, but it's still not
perfect - the amplitude of the output has decreased relative to the
input, and there is a non-linearity and a phase offset.

I also tried with Vg as a 2Vpp sinewave at a 6V offset - so that Vgs is
always 5V, ie:

Vdc gate GND SIN(6 1 1000k 0 0)

The results are shown here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-1mhz-6Voffset.pdf

It's better than the Vg=7V case, but there are still problems - mainly
with the amplitude.

The FET has a Rds(on) = 70 Ohm, and the load is 1MOhm Also, the maximum
Vin as seen in the results from applying a 1mhz sinewave on Vg is
1.9995V. So a potential divider effect would be expected, and the
maximum Vout should be 1.99936V.

However, the maximum Vout as measured in the second set of results
above is actually 1.8303V. For this to be the case, it must be dropping
169.2mV across the FET, which means the FET Rds(on) must be 92.44kOhm,
when Vgs=5V. This can't be correct.

So I'm still not sure about what is going on. Any ideas?

Thanks to everyone for their replys,

Steve

 

[Jim Thompson]

Steve, you need to look at page 2 of the datasheet, in the rows labelled
"Drain-Source On-Resistance" There you'll see the details of Joerg's
description. Now, if your gate voltage is high enough above the highest
signal voltage, the fet remains low-resistance.

In your 5v gate plot, however, the peaks of the signal cause the source
voltage to approach the gate voltage so that the fet resistance rises
high enough to change the signal going to your output. You don't say
what your circuit is, but your output waveform is about right for this
effect.

How did you manage to get the fets to survive a 100V gate voltage? They
should all have fried instantly (p. 2, absolute maximum says +30, -25).
Are all your fets shorted now? You should check drain-source
resistance with Vgs = 0. They're probably dead.

John Perry

Steve, If you want to get fancy, you can create a _nearly_ constant
Ron by adding the signal to a your control voltage with an OpAmp and
applying the sum to the gate, producing a constant Vgs.

...Jim Thompson

 

[Joerg]

Hello Jim,

Steve, If you want to get fancy, you can create a _nearly_ constant
Ron by adding the signal to a your control voltage with an OpAmp and
applying the sum to the gate, producing a constant Vgs.

But at 2nsec the opamp might require a call to the local utility before
turning it on, and maybe a 2nd mortgage ;-)

Regards, Joerg

 

[Joerg]

Hello Steve,

I've re-run the simulations to see whether this is the case. First, I
tried with Vg=7V, so that Vgs never drops below 5V. The results are
here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-7V.pdf

That doesn't look too bad. You'll need more Vgs to reduce RDSon modulation.

I also tried with Vg as a 2Vpp sinewave at a 6V offset - so that Vgs is
always 5V, ie:

Vdc gate GND SIN(6 1 1000k 0 0)

The results are shown here:

http://www.teamlinux.org.uk/steve/spice/switch_Vg-1mhz-6Voffset.pdf

It's better than the Vg=7V case, but there are still problems - mainly
with the amplitude.

That plot doesn't look bad at all.

The FET has a Rds(on) = 70 Ohm, and the load is 1MOhm Also, the maximum
Vin as seen in the results from applying a 1mhz sinewave on Vg is
1.9995V. So a potential divider effect would be expected, and the
maximum Vout should be 1.99936V.

However, the maximum Vout as measured in the second set of results
above is actually 1.8303V. For this to be the case, it must be dropping
169.2mV across the FET, which means the FET Rds(on) must be 92.44kOhm,
when Vgs=5V. This can't be correct.

So I'm still not sure about what is going on. Any ideas?

Look at what the capacitive load is, mostly to the substrate. At 1MHz
that does matter, depending on your source impedance.

Quite frankly my faith in SPICE when it comes to simulating FETs is a
bit limited. I usually go by my "paper computer" and a good scope.

While I used to be a big fan of the SD5400 my usage of them in designs
has fizzled. The price increases are the main reason, lack of stock at
some suppliers is another concern I have. There are other ways to switch
a signal path fast. One is a diode array and a toroid transformer. Since
quad arrays are often in the "boutique part" category, expensive and
hard to procure I often squeeze by with pairs. Those cost pennies.

Then there are lots of monolithic switches for wireless gear. Look under
T/R switches and diversity switches.

Regards, Joerg

 

[Jim Thompson]

Hello Jim,


But at 2nsec the opamp might require a call to the local utility before
turning it on, and maybe a 2nd mortgage ;-)

Regards, Joerg

Details, Details ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

Details, Details ;-)

That's what somebody said to me when using their pool heater in winter.
Until the propane bill arrived, that is.

Your idea can be implemented cheaply though. Just use a 1:1 toroid
transformer and stack the secondary in series with the gate control source.

Regards, Joerg

 

[Jim Thompson]

Hello Jim,

That's what somebody said to me when using their pool heater in winter.
Until the propane bill arrived, that is.

Your idea can be implemented cheaply though. Just use a 1:1 toroid
transformer and stack the secondary in series with the gate control source.

Regards, Joerg

Yep, or use current drive.

Come to think of it I used transformer drive on the Hubble, with DC
restoration games so I could PWM. That was BC&S (before computers and
simulators), I'll see if I have a paper copy somewhere.

...Jim Thompson